Variable function information processor

ABSTRACT

There can be provided a variable function information processor in which a logic module ( 10 ) with the further decreased number of transistors used in the logic module constituting the variable function information processor is provided, a function of being able to realize both a combinational logic circuit for-performing a full addition operation of input signals in accordance with a control signal and outputting the sum and a sequential circuit for temporarily holding the input signal to delay the signal and outputting it by the same logic module is provided, and in a semiconductor circuit element group for constituting the combinational logic circuit and the sequential circuit, a common part of the combinational logic circuit and the sequential circuit is used for both the circuits, whereby the number of elements can be further decreased, and the resources of the variable function information processor can be effectively exploited.

TECHNICAL FIELD

[0001] The present invention relates to a variable function informationprocessor.

BACKGROUND ART

[0002] Conventionally, there exists a variable function informationprocessing circuit whose circuit configuration can be changed by beingdefined. Also, there exists a variable function information processorusing the variable function information processing circuit. A logicmodule constituting the variable function information processing circuitused in the conventional variable function information processorconstitutes an information processing circuit for performing desiredprocessing by a method of performing a combinational logic operation bya certain part of an arithmetic circuit in the logic module andperforming a sequential operation by another certain part of thearithmetic circuit. Namely, the logic module constituting theconventional variable function information processing circuit isstructured to include a part for performing a combinational logicoperation and a part for performing a sequential operation differentfrom the part for performing the combinational logic operation.

[0003] Therefore, when the logic module is used for a certaincombinational logic operation (the part for performing the combinationallogic operation is used), the part of the arithmetic circuit forperforming the sequential operation is not used, and similarly, when thelogic module is used for a certain sequential operation (the part forperforming the sequential operation is used), the part of the arithmeticcircuit for performing the combinational logic operation is not used.Hence, when a variable function information processor for performingdesired processing is structured using the variable function informationprocessing circuit, the resources of the variable function informationprocessor are not effectively exploited, thereby causing waste.

[0004] As a logic module to solve this problem, the invention disclosedin Japanese Patent Laid-open No. 9-284124 (hereinafter referred to as “aconventional example”) is given. In the conventional example, a logicmodule is structured so as to perform a combinational logic operationfunction of more than 2,200 Boolean algebras or perform a sequentialoperation function of a D-type latch or D-type flip-flop, and both acombinational circuit and a sequential circuit are formed by using thelogic module, whereby a space on a gate array is efficiently used.

[0005] The logic module in the conventional example is, however,composed of three two-input multiplexers and three two-inputmultiplexers with inverting inputs, and uses 42 transistors in total.The smaller the number of transistors constituting one logic module, themore the number of logic modules integrated on one LSI chip becomes,whereby a high-performance and advanced information processor can berealized. Accordingly, it is preferable that the number of transistorsconstituting a logic module be smaller.

SUMMARY OF THE INVENTION

[0006] A problem to be solved of the present invention is to provide avariable function information processor which uses a logic module withthe further decreased number of transistors to be used in order thatlogic modules constituting the variable function information processorare increased in number, that is, integrated at a high degree ofintegration.

[0007] Another problem to be solved of the present invention is torealize both a combinational logic circuit and a sequential circuit bythe same logic module, whereby the resources of a variable functioninformation processor are effectively exploited.

[0008] A variable function information processor of the presentinvention is characterized by comprising: at least one basic circuitblock composed of a two-input arithmetic circuit structured by atwo-input exclusive-NOR circuit or a two-input exclusive-OR circuit, towhich a first signal is inputted as one input signal from a first inputterminal, an inverter for inverting an output signal of the two-inputarithmetic circuit, a switching circuit for transmitting an outputsignal of the inverter or a second signal inputted from a second inputterminal as the other input signal to the two-input arithmetic circuitin accordance with a third signal inputted from a third input terminal,and an output terminal capable of outputting at least either the outputsignal of the two-input arithmetic circuit or the output signal of theinverter; an input terminal group including the first to third inputterminals; an output terminal group including the output terminal; and asemiconductor arithmetic circuit electrically connected to the inputterminal group, the output terminal group, and the basic circuit block,wherein a function of serving both as a combinational logic circuit forperforming a logical operation of the input signals and as a sequentialcircuit for performing a sequential operation of the input signalaccording to the input signals inputted from the input terminal group isprovided, and through the use of the basic circuit block, in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.

[0009] Another aspect of the variable function information processor ofthe present invention is characterized in that the semiconductorarithmetic circuit includes an output switching circuit for selectivelyoutputting any of the input signals inputted from the input terminalgroup.

[0010] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a first two-input arithmetic circuit structured by a firsttwo-input exclusive-NOR circuit or a first two-input exclusive-ORcircuit, to which a first signal is inputted as one input signal from afirst input terminal; a first inverter for inverting an output signal ofthe first two-input arithmetic circuit; and a first switching circuitfor transmitting an output signal of the first inverter or a secondsignal inputted from a second input terminal as the other input signalto the first two-input arithmetic circuit in accordance with a thirdsignal inputted from a third input terminal, the first basic circuitblock outputting the output signal of the first two-input arithmeticcircuit or the output signal of the first inverter as an output signalof the first basic circuit block, the second basic circuit blockincludes: a second two-input arithmetic circuit structured by a secondtwo-input exclusive-NOR circuit or a second two-input exclusive-ORcircuit, to which a fourth signal is inputted as one input signal from afourth input terminal; a second inverter for inverting an output signalof the second two-input arithmetic circuit; and a second switchingcircuit for transmitting an output signal of the second inverter or theoutput signal of the first basic circuit block as the other input signalto the second two-input arithmetic circuit in accordance with a fifthsignal inputted from a fifth input terminal, the second basic circuitblock outputting the output signal of the second two-input arithmeticcircuit or the output signal of the second inverter via a first externaloutput terminal, the semiconductor arithmetic circuit transmits a sixthsignal inputted from a sixth input terminal or a seventh signal inputtedfrom a seventh input terminal to a second external output terminal inaccordance with at least either the output signal of the first two-inputarithmetic circuit or the output signal of the first inverter, afunction of serving both as a combinational logic circuit for performinga full addition operation of the input signals and outputting a resultof the operation and as a sequential circuit for temporarily holding theinput signal to delay the input signal and outputting it according tothe input signals inputted from the first to seventh input terminals isprovided, and that in a semiconductor circuit element group forconstituting the combinational logic circuit and the sequential circuit,a common part of the combinational logic circuit and the sequentialcircuit is used for both the circuits.

[0011] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a first two-input exclusive-NOR circuit, to which a firstsignal is inputted as one input signal from a first input terminal; afirst inverter for inverting an output signal of the first two-inputexclusive-NOR circuit; and a first switching circuit for transmitting anoutput signal of the first inverter or a second signal inputted from asecond input terminal as the other input signal to the first two-inputexclusive-NOR circuit in accordance with a third signal inputted from athird input terminal, the second basic circuit block includes: a secondtwo-input exclusive-NOR circuit, to which a fourth signal is inputted asone input signal from a fourth input terminal, for outputting an outputsignal via a first external output terminal; a second inverter forinverting the output signal of the second two-input exclusive-NORcircuit; and a second switching circuit for transmitting an outputsignal of the second inverter or the output signal of the firsttwo-input exclusive-NOR circuit as the other input signal to the secondtwo-input exclusive-NOR circuit in accordance with a fifth signalinputted from a fifth input terminal, the semiconductor arithmeticcircuit transmits a sixth signal inputted from a sixth input terminal ora seventh signal inputted from a seventh input terminal to a secondexternal output terminal in accordance with at least either the outputsignal of the first two-input exclusive-NOR circuit or the output signalof the first inverter, a function of serving both as a combinationallogic circuit for performing a full addition operation of the inputsignals and outputting a result of the operation and as a sequentialcircuit for temporarily holding the input signal to delay the inputsignal and outputting it according to the input signals inputted fromthe first to seventh input terminals is provided, and that in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.

[0012] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a two-input exclusive-NOR circuit, to which a first signal isinputted as one input signal from a first input terminal; a firstinverter for inverting an output signal of the first two-inputexclusive-NOR circuit; and a first switching circuit for transmitting anoutput signal of the first inverter or a second signal inputted from asecond input terminal as the other input signal to the two-inputexclusive-NOR circuit in accordance with a third signal inputted from athird input terminal, the second basic circuit block includes: atwo-input exclusive-OR circuit, to which a fourth signal is inputted asone input signal from a fourth input terminal; a second inverter forinverting an output signal of the two-input exclusive-OR circuit andoutputting an output signal via a first external output terminal; and asecond switching circuit for transmitting the output signal of thesecond inverter or the output signal of the two-input exclusive-NORcircuit as the other input signal to the two-input exclusive-OR circuitin accordance with a fifth signal inputted from a fifth input terminal,the semiconductor arithmetic circuit transmits a sixth signal inputtedfrom a sixth input terminal or a seventh signal inputted from a seventhinput terminal to a second external output terminal in accordance withat least either the output signal of the two-input exclusive-NOR circuitor the output signal of the first inverter, a function of serving bothas a combinational logic circuit for performing a full additionoperation of the input signals and outputting a result of the operationand as a sequential circuit for temporarily holding the input signal todelay the input signal and outputting it according to the input signalsinputted from the first to seventh input terminals is provided, and thatin a semiconductor circuit element group for constituting thecombinational logic circuit and the sequential circuit, a common part ofthe combinational logic circuit and the sequential circuit is used forboth the circuits.

[0013] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a two-input exclusive-OR circuit, to which a first signal isinputted as one input signal from a first input terminal; a firstinverter for inverting an output signal of the two-input exclusive-ORcircuit; and a first switching circuit for transmitting an output signalof the first inverter or a second signal inputted from a second inputterminal as the other input signal to the two-input exclusive-OR circuitin accordance with a third signal inputted from a third input terminal,the second basic circuit block includes: a two-input exclusive-NORcircuit, to which a fourth signal is inputted as one input signal from afourth input terminal, for outputting an output signal via a firstexternal output terminal; a second inverter for inverting the outputsignal of the two-input exclusive-NOR circuit; and a second switchingcircuit for transmitting an output signal of the second inverter or theoutput signal of the first inverter as the other input signal to thetwo-input exclusive-NOR circuit in accordance with a fifth signalinputted from a fifth input terminal, the semiconductor arithmeticcircuit transmits a sixth signal inputted from a sixth input terminal ora seventh signal inputted from a seventh input terminal to a secondexternal output terminal in accordance with at least either the outputsignal of the two-input exclusive-OR circuit or the output signal of thefirst inverter, a function of serving both as a combinational logiccircuit for performing a full addition operation of the input signalsand outputting a result of the operation and as a sequential circuit fortemporarily holding the input signal to delay the input signal andoutputting it according to the input signals inputted from the first toseventh input terminals is provided, and that in a semiconductor circuitelement group for constituting the combinational logic circuit and thesequential circuit, a common part of the combinational logic circuit andthe sequential circuit is used for both the circuits.

[0014] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a first two-input exclusive-OR circuit, to which a firstsignal is inputted as one input signal from a first input terminal; afirst inverter for inverting an output signal of the first two-inputexclusive-OR circuit; and a first switching circuit for transmitting anoutput signal of the first inverter or a second signal inputted from asecond input terminal as the other input signal to the first two-inputexclusive-OR circuit in accordance with a third signal inputted from athird input terminal, the second basic circuit block includes: a secondtwo-input exclusive-OR circuit, to which a fourth signal is inputted asone input signal from a fourth input terminal; a second inverter forinverting an output signal of the second two-input exclusive-OR circuitand outputting an output signal via a first external output terminal;and a second switching circuit for transmitting the output signal of thesecond inverter or the output signal of the first inverter as the otherinput signal to the second two-input exclusive-OR circuit in accordancewith a fifth signal inputted from a fifth input terminal, thesemiconductor arithmetic circuit transmits a sixth signal inputted froma sixth input terminal or a seventh signal inputted from a seventh inputterminal to a second external output terminal in accordance with atleast either the output signal of the first two-input exclusive-ORcircuit or the output signal of the first inverter, a function ofserving both as a combinational logic circuit for performing a fulladdition operation of the input signals and outputting a result of theoperation and as a sequential circuit for temporarily holding the inputsignal to delay the input signal and outputting it according to theinput signals inputted from the first to seventh input terminals isprovided, and that in a semiconductor circuit element group forconstituting the combinational logic circuit and the sequential circuit,a common part of the combinational logic circuit and the sequentialcircuit is used for both the circuits.

[0015] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a first two-input exclusive-NOR circuit, to which a firstsignal is inputted as one input signal from a first input terminal; afirst inverter for inverting an output signal of the first two-inputexclusive-NOR circuit; and a first switching circuit for transmitting anoutput signal of the first inverter or a second signal inputted from asecond input terminal as the other input signal to the first two-inputexclusive-NOR circuit in accordance with a third signal inputted from athird input terminal, the second basic circuit block includes: a secondtwo-input exclusive-NOR circuit, to which a fourth signal is inputted asone input signal from a fourth input terminal; a second inverter forinverting an output signal of the two-input exclusive-NOR circuit andoutputting an output signal via a first external output terminal; and asecond switching circuit for transmitting the output signal of thesecond inverter or the output signal of the first inverter as the otherinput signal to the second two-input exclusive-NOR circuit in accordancewith a fifth signal inputted from a fifth input terminal, thesemiconductor arithmetic circuit transmits a sixth signal inputted froma sixth input terminal or a seventh signal inputted from a seventh inputterminal to a second external output terminal in accordance with atleast either the output signal of the first two-input exclusive-NORcircuit or the output signal of the first inverter, a function ofserving both as a combinational logic circuit for performing a fulladdition operation of the input signals and outputting a result of theoperation and as a sequential circuit for temporarily holding the inputsignal to delay the input signal and outputting it according to theinput signals inputted from the first to seventh input terminals isprovided, and that in a semiconductor circuit element group forconstituting the combinational logic circuit and the sequential circuit,a common part of the combinational logic circuit and the sequentialcircuit is used for both the circuits.

[0016] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a two-input exclusive-NOR circuit, to which a first signal isinputted as one input signal from a first input terminal; a firstinverter for inverting an output signal of the two-input exclusive-NORcircuit; and a first switching circuit for transmitting an output signalof the first inverter or a second signal inputted from a second inputterminal as the other input signal to the two-input exclusive-NORcircuit in accordance with a third signal inputted from a third inputterminal, the second basic circuit block includes: a two-inputexclusive-OR circuit, to which a fourth signal is inputted as one inputsignal from a fourth input terminal and outputting an output signal viaa first external output terminal; a second inverter for inverting theoutput signal of the two-input exclusive-OR circuit; and a secondswitching circuit for transmitting an output signal of the secondinverter or the output signal of the first inverter as the other inputsignal to the two-input exclusive-OR circuit in accordance with a fifthsignal inputted from a fifth input terminal, the semiconductorarithmetic circuit transmits a sixth signal inputted from a sixth inputterminal or a seventh signal inputted from a seventh input terminal to asecond external output terminal in accordance with at least either theoutput signal of the two-input exclusive-NOR circuit or the outputsignal of the first inverter, a function of serving both as acombinational logic circuit for performing a full addition operation ofthe input signals and outputting a result of the operation and as asequential circuit for temporarily holding the input signal to delay theinput signal and outputting it according to the input signals inputtedfrom the first to seventh input terminals is provided, and that in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.

[0017] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a two-input exclusive-OR circuit, to which a first signal isinputted as one input signal from a first input terminal; a firstinverter for inverting an output signal of the two-input exclusive-ORcircuit; and a first switching circuit for transmitting an output signalof the first inverter or a second signal inputted from a second inputterminal as the other input signal to the two-input exclusive-OR circuitin accordance with a third signal inputted from a third input terminal,the second basic circuit block includes: a two-input exclusive-NORcircuit, to which a fourth signal is inputted as one input signal from afourth input terminal; a second inverter for inverting the output signalof the two-input exclusive-NOR circuit and outputting an output signalvia a first external output terminal; and a second switching circuit fortransmitting the output signal of the second inverter or the outputsignal of the two-input exclusive-OR circuit as the other input signalto the second two-input exclusive-NOR circuit in accordance with a fifthsignal inputted from a fifth input terminal, the semiconductorarithmetic circuit transmits a sixth signal inputted from a sixth inputterminal or a seventh signal inputted from a seventh input terminal to asecond external output terminal in accordance with at least either theoutput signal of the two-input exclusive-OR circuit or the output signalof the first inverter, a function of serving both as a combinationallogic circuit for performing a full addition operation of the inputsignals and outputting a result of the operation and as a sequentialcircuit for temporarily holding the input signal to delay the inputsignal and outputting it according to the input signals inputted fromthe first to seventh input terminals is provided, and that in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.

[0018] Another aspect of the variable function information processor ofthe present invention is characterized in that a first and a secondbasic circuit block are provided, and the first basic circuit blockincludes: a first two-input exclusive-OR circuit, to which a firstsignal is inputted as one input signal from a first input terminal; afirst inverter for inverting an output signal of the first two-inputexclusive-OR circuit; and a first switching circuit for transmitting anoutput signal of the first inverter or a second signal inputted from asecond input terminal as the-other input signal to the first two-inputexclusive-OR circuit in accordance with a third signal inputted from athird input terminal, the second basic circuit block includes: a secondtwo-input exclusive-OR circuit, to which a fourth signal is inputted asone input signal from a fourth input terminal, for outputting an outputsignal via a first external output terminal; a second inverter forinverting the output signal of the second two-input exclusive-ORcircuit; and a second switching circuit for transmitting an outputsignal of the second inverter or-the output signal of the firsttwo-input exclusive-OR circuit as the other input signal to the secondtwo-input exclusive-OR circuit in accordance with a fifth signalinputted from a fifth input terminal, the semiconductor arithmeticcircuit transmits a sixth signal inputted from a sixth input terminal ora seventh signal inputted from a seventh input terminal to a secondexternal output terminal in accordance with at least either the outputsignal of the first two-input exclusive-OR circuit or the output signalof the first inverter, a function of serving both as a combinationallogic circuit for performing a full addition operation of the inputsignals and outputting a result of the operation and as a sequentialcircuit for temporarily holding the input signal to delay the inputsignal and outputting it according to the input signals inputted fromthe first to seventh input terminals is provided, and that in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.

[0019] Another aspect of the variable function information processor ofthe present invention is characterized in that the variable functioninformation processor further comprises a third two-input arithmeticcircuit structured by a third two-input exclusive-NOR circuit or a thirdtwo-input exclusive-OR circuit, whose output terminal is electricallyconnected to at least one of the first to seventh input terminals, afunction of serving both as a combinational logic circuit for performingan addition operation or a subtraction operation of a set of the inputsignals and outputting a result of the operation and as a sequentialcircuit for temporarily holding the input signal to delay the inputsignal and outputting it according to input signals inputted from inputterminals for inputting input signals to the third two-input arithmeticcircuit and the first to seventh input terminals is provided, and thatin a semiconductor circuit element group for constituting thecombinational logic circuit and the sequential circuit, a common part ofthe combinational logic circuit and the sequential circuit is used forboth the circuits.

[0020] Another aspect of-the variable function information processor ofthe present invention is characterized in that a plurality of theaforementioned variable function information processors are provided andelectrically connected to one another directly or via a semiconductorarithmetic circuit, whereby a new input terminal group is formed by aplurality of input terminals through which input signals are allowed tobe inputted from the outside to the variable function informationprocessor, and a new output terminal group is formed by a plurality ofoutput terminals through which output signals are allowed to be inputtedfrom the variable function information processor to the outside, afunction of serving both as a combinational logic circuit and asequential circuit according to the input signals inputted from theinput terminal group is provided, and that in a semiconductor circuitelement group to constitute the combinational logic circuit and thesequential circuit, a common part of the combinational logic circuit andthe sequential circuit is used for both the circuits.

[0021] Another aspect of the variable function information processor ofthe present invention is characterized in that the variable functioninformation processor comprises: at least one basic circuit blockcomposed of a two-input arithmetic circuit, to which a first signal isinputted as one input signal from a first input terminal, for outputtingan operation result of a predetermined logical operation of the firstsignal and the other input signal or an inverted signal of the otherinput signal according to the first signal, an inverter for invertingthe output signal of the two-input arithmetic circuit, a switchingcircuit for selectively supplying an output signal of the inverter or asecond signal inputted from a second input terminal as the other inputsignal to the two-input arithmetic circuit in accordance with a thirdsignal inputted from a third input terminal, and an output terminalcapable of outputting at least either the output signal of the two-inputarithmetic circuit or the output signal of the inverter, the basiccircuit block serving both as a combinational logic circuit and as asequential circuit according to the input signals inputted from thefirst to third input terminals, and in semiconductor circuit elements tofunction as the combinational logic circuit and the sequential circuitrespectively, sharing a common circuit element between both thecircuits.

[0022] Another aspect of the variable function information processor ofthe present invention is characterized in that a plurality of the basiccircuit blocks are provided, and that on the occasion of subordinateconnection, the output terminal of the basic circuit block in apreceding stage is connected to the second input terminal of the basiccircuit block in a subsequent stage.

[0023] Another aspect of the variable function information processor ofthe present invention is characterized in that the two-input arithmeticcircuit is a two-input exclusive-NOR circuit or a two-input exclusive-ORcircuit.

[0024] Another aspect of the variable function information processor ofthe present invention is characterized in that the basic circuit blockfunctions as an adding circuit or a latch circuit according to the inputsignal inputted from the first input terminal.

[0025] Another aspect of the variable function information processor ofthe present invention is characterized in that the variable functioninformation processor further comprises: a semiconductor arithmeticcircuit for performing predetermined processing in response to a signalinputted; and an external output terminal capable of outputting anoutput signal of the semiconductor arithmetic circuit, the semiconductorarithmetic circuit performing the predetermined processing in responseto at least any one signal of the input signal inputted from the firstto third input terminals or an external input terminal, the outputsignal of the two-input arithmetic circuit, and the output signal of theinverter.

[0026] Another aspect of the variable function information processor ofthe present invention is characterized in that the semiconductorarithmetic circuit includes an output switching circuit for outputtingthe input signal inputted from the first to third input terminals or theexternal input terminal according to at least either the output signalof the two-input arithmetic circuit or the output signal of theinverter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a first embodiment of the present invention;

[0028]FIG. 2 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the first embodiment of the present invention;

[0029]FIG. 3 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the first embodiment of the presentinvention;

[0030]FIG. 4 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the first embodiment of the presentinvention;

[0031]FIG. 5 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a second embodiment of the present invention;

[0032]FIG. 6 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the second embodiment of the present invention;

[0033]FIG. 7 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the second embodiment of the presentinvention;

[0034]FIG. 8 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the second embodiment of the presentinvention;

[0035]FIG. 9 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a third embodiment of the present invention;

[0036]FIG. 10 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the third embodiment of the present invention;

[0037]FIG. 11 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the third embodiment of the presentinvention;

[0038]FIG. 12 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the third embodiment of the presentinvention;

[0039]FIG. 13 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a fourth embodiment of the present invention;

[0040]FIG. 14 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the fourth embodiment of the present invention;

[0041]FIG. 15 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the fourth embodiment of the presentinvention;

[0042]FIG. 16 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the fourth embodiment of the presentinvention;

[0043]FIG. 17 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a fifth embodiment of the present invention;

[0044]FIG. 18 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the fifth embodiment of the present invention;

[0045]FIG. 19 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the fifth embodiment of the presentinvention;

[0046]FIG. 20 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the fifth embodiment of the presentinvention;

[0047]FIG. 21 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a sixth embodiment of the present invention;

[0048]FIG. 22 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the sixth embodiment of the present invention;

[0049]FIG. 23 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the sixth embodiment of the presentinvention;

[0050]FIG. 24 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the sixth embodiment of the presentinvention;

[0051]FIG. 25 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a seventh embodiment of the present invention;

[0052]FIG. 26 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the seventh embodiment of the present invention;

[0053]FIG. 27 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the seventh embodiment of the presentinvention;

[0054]FIG. 28 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the seventh embodiment of the presentinvention;

[0055]FIG. 29 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to an eighth embodiment of the present invention;

[0056]FIG. 30 is a diagram showing another example of the configurationof the logic module constituting the variable function informationprocessor according to the eighth embodiment of the present invention;

[0057]FIG. 31 is a diagram showing still another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the eighth embodiment of the presentinvention;

[0058]FIG. 32 is a diagram showing yet another example of theconfiguration of the logic module constituting the variable functioninformation processor according to the eighth embodiment of the presentinvention;

[0059]FIG. 33A and FIG. 33B are diagrams each showing an example of aconfiguration of a two-input exclusive-NOR circuit;

[0060]FIG. 34A and FIG. 34B are diagrams each showing an example of aconfiguration of a two-input exclusive-OR circuit;

[0061]FIG. 35 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a ninth embodiment of the present invention;

[0062]FIG. 36 is a diagram showing an example of a configuration of alogic module constituting a variable function information processoraccording to a tenth embodiment of the present invention; and

[0063]FIG. 37 is a diagram showing an example of a configuration of avariable function information processor according to an eleventhembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0064] Embodiments will be given below to explain the present inventionin detail, but it is needless to say that the present invention is notlimited to these embodiments. Features, properties, and variousadvantages of the present invention, however, will become more apparentfrom the accompanying drawings and the following detailed description ofpreferred embodiments.

[0065] The embodiments of the present invention will be explained belowbased on the drawings.

First Embodiment

[0066] Regarding a logic module constituting a variable functioninformation processor according to the first embodiment of the presentinvention, its configuration and operation will be explained.

[0067]FIG. 1 is a diagram showing an example of the configuration of thelogic module in the first embodiment.

[0068] In FIG. 1, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither of them selectively becomes ON according to a signal Sd inputtedfrom an input terminal D to transmit the signal Sa or the output signalof the inverter 16 to a two-input exclusive-NOR circuit 14 as one inputsignal. The other input signal of the two-input exclusive-NOR circuit 14is a signal Se inputted from an input terminal E. An output signal ofthe two-input exclusive-NOR circuit 14 (a signal outputted as a resultof an operation by the two-input exclusive-NOR circuit 14) is inputtedas an input signal to the inverter 16.

[0069] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the two-inputexclusive-NOR circuit 14. The switching circuits 12 a and 12 b aredesigned to selectively become ON according to a signal Sf inputted froman input terminal F and transmit the output signal of the inverter 17 orthe output signal of the two-input exclusive-NOR circuit 14 to atwo-input exclusive-NOR circuit 15 as one input signal. The other inputsignal of the two-input exclusive-NOR circuit 15 is a signal Sg inputtedfrom an input terminal G. An output signal of the two-inputexclusive-NOR circuit 15 is inputted as an input signal to the inverter17.

[0070] Further, an output terminal of the two-input exclusive-NORcircuit 15 and an output terminal X of a logic module 10 are connectedto each other, and the output signal of the two-input exclusive-NORcircuit 15 is outputted as an output signal Sx of the logic module 10.Furthermore, the output signal of the two-input exclusive-NOR circuit 14is supplied to switching circuits 13 a and 13 b respectively. Theswitching circuits 13 a and 13 b are controlled by the output signal ofthe two-input exclusive-NOR circuit 14 so that a signal Sb inputted froman input terminal B or a signal Sc inputted from an input terminal C isselectively transmitted to an output terminal Y. Thus, the signal Sb orSc transmitted selectively is outputted from the output terminal Y as anoutput signal Sy of the logic module 10.

[0071] In FIG. 1, a logic high (high-level signal) is applied to theswitching circuits 11 a and 11 b from the input terminal D and a logiclow (low-level signal) is applied to the switching circuits 12 a and 12b from the input terminal F so that the switching circuits 11 a and 12 bbecome ON and that the switching circuits 11 b and 12 a become OFF.Moreover, an input signal Ia is inputted from the input terminal A, aninput signal Ib is inputted from each of the input terminals B and E,and similarly an input signal Ic is inputted from each of the inputterminals C and G. On this occasion, a sum and a carry of the inputsignals Ia, Ib, and Ic are outputted respectively as the output signalsSx (sum) and Sy (carry) from the output terminals X and Y. Namely, thelogic module 10 operates as a full adding circuit of a combinationallogic circuit.

[0072] More specifically, the input signal Ia and the input signal Iaare operated in the two-input exclusive-NOR circuit 14, and an operationresult in the two-input exclusive-NOR circuit 14 (negation of the sum ofthe input signal Ia and the input signal Ib) and the input signal Ic areoperated in the two-input exclusive-NOR circuit 15. An operation resultin the two-input exclusive-NOR circuit 15 is outputted as the outputsignal Sx from the output terminal X. When logical values of the inputsignal Ia and the input signal Ia are the same, the switching circuit 13a is ON and the switching circuit 13 b is OFF, whereby the input signalIa is outputted as the output signal Sy from the output terminal Y. Whenthey are different, the switching circuit 13 a is OFF and the switchingcircuit 13 b is ON, whereby the input signal Ic is outputted as theoutput signal Sy from the output terminal Y. Namely, when both of theinput signals Ia and Ib are “0” or “1”, irrespective of the input signalIc, the input signal Ib is outputted as a carry of the input signals Ia,Ib, and Ic from the output terminal Y. When one of the input signals Iaand Ib is “0” and the other is “1”, the input signal Ic is outputted asa carry of the input signals Ia, Ib, and Ic from the output terminal Y.

[0073] Moreover, in FIG. 1, logic lows are applied from the inputterminals E and G to the two-input exclusive-NOR circuits 14 and 15respectively so that the two-input exclusive-NOR circuits 14 and 15substantially operate as inverters, and clock signals are inputted fromthe input terminals D and F to the switching circuits 11 a and 11 b ,and 12 a and 12 b . On this occasion, the input signal Ia inputted fromthe input terminal A is delayed in synchronization with the clocksignals and outputted as the output signal Sx from the output terminalX. In other words, the logic module 10 operates as a delay circuit(D-type flip-flop) of a sequential circuit. Incidentally, when the logicmodule 10 is operated as the delay circuit of the sequential circuit,input signals inputted from the input terminals B and C are optional.

[0074] The cases where the logic module shown in FIG. 1 operates as thefull adding circuit (full adder) and operates as the delay circuit(D-type flip-flop) are explained above, but operations by the logicmodule shown in FIG. 1 are not limited to the aforementioned twooperations. It is needless to say that in the logic module in the firstembodiment of the present invention, by inputting predetermined inputsignals from the input terminals A to G, various kinds of combinationallogic circuits including a selector circuit which selects any one ofinputted input signals and outputs it, for example, can be realized.

[0075]FIG. 2 to FIG. 4 are diagrams showing other examples of theconfiguration of the logic module in the first embodiment.

[0076] The logic module 10 shown in each of FIG. 2 to FIG. 4 and thelogic module 10 shown in FIG. 1 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configurations ofthe logic modules 10 shown in FIG. 2 to FIG. 4 and the configuration ofthe logic module 10 shown in FIG. 1 are different from each other. Thesignal for controlling the switching circuits 13 a and 13 b is theoutput signal of the inverter 16 in the logic module 10 shown in FIG. 2,but both the output signal of the two-input exclusive-NOR circuit 14 andthe output signal of the inverter 16 in the logic module 10 shown ineach of FIG. 3 and FIG. 4. Moreover, with the difference between thesignals for controlling the switching circuits 13 a and 13 b , logicvalues (a logic high, a logic low) at which the switching circuits 13 aand 13 b operate also differ according to supplied signals.

[0077] It should be mentioned that the operations of the logic modules10 shown in FIG. 2 to FIG. 4 are the same as that of the logic moduleshown in FIG. 1.

[0078] As explained above, according to the first embodiment, byconfiguring the logic module 10 as shown in each of FIG. 1 to FIG. 4,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0079] In this case, the two-input exclusive-NOR circuits 14 and 15shown in FIG. 1 to FIG, 4 can be structured, for example, by circuitsshown in FIG. 33A and FIG. 33B. FIG. 33A and FIG. 33B are diagrams eachshowing an example of the two-input exclusive-NOR circuit. Incidentally,the configurations and operations of the two-input exclusive-NORcircuits shown in FIG. 33A and FIG. 33B will be described later. Byusing such a circuit as shown in FIG. 33A or FIG. 33B, the two-inputexclusive-NOR circuits 14 and 15 each can be composed of fourtransistors, whereby the number of transistors composing the logicmodule 10 can be effectively decreased.

[0080] In the logic module 10 in the first embodiment shown in each ofFIG. 1 to FIG. 4, the number of transistors necessary to constitute thelogic module 10 is 18, and consequently a function almost equal to thatin the aforementioned conventional example can be realized by the numberof transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Second Embodiment

[0081] Next, regarding a logic module constituting a variable functioninformation processor according to the second embodiment of the presentinvention, its configuration and operation will be explained.

[0082]FIG. 5 is a diagram showing an example of the configuration of thelogic module in the second embodiment.

[0083] In FIG. 5, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither of them selectively becomes ON according to a signal Sd inputtedfrom an input terminal D to transmit the signal Sa or the output signalof the inverter 16 to a two-input exclusive-NOR circuit 14 as one inputsignal. The other input signal of the two-input exclusive-NOR circuit 14is a signal Se inputted from an input terminal E. An output signal ofthe two-input exclusive-NOR circuit 14 is inputted to the inverter 16 asan input signal.

[0084] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the two-inputexclusive-NOR circuit 14. The switching circuits 12 a and 12 b aredesigned to selectively become ON according to a signal Sf inputted froman input terminal F and transmit the output signal of the inverter 17 orthe output signal of the two-input exclusive-NOR circuit 14 to atwo-input exclusive-OR circuit 19 as one input signal. The other inputsignal of the two-input exclusive-OR circuit 19 is a signal Sg inputtedfrom an input terminal G. An output signal of the two-input exclusive-ORcircuit 19 is inputted to the inverter 17 as an input signal.

[0085] Further, an output terminal of the inverter 17 and an outputterminal X of a logic module 10 are connected to each other, and theoutput signal of the inverter 17 is outputted as an output signal Sx ofthe logic module 10. Furthermore, the output signal of the two-inputexclusive-NOR circuit 14 is supplied to switching circuits 13 a and 13 brespectively. The switching circuits 13 a and 13 b are controlled by theoutput signal of the two-input exclusive-NOR circuit 14 so that a signalSb inputted from an input terminal B or a signal Sc inputted from aninput terminal C is selectively transmitted to an output terminal Y.Thus, the signal Sb or Sc transmitted selectively is outputted as anoutput signal Sy of the logic module 10 from the output terminal Y.

[0086] In FIG. 5, a logic high is applied to the switching circuits 11 aand 11 b from the input terminal D and a logic low is applied to theswitching circuits 12 a and 12 b from the input terminal F so that theswitching circuits 11 a and 12 b become ON and that the switchingcircuits 11 b and 12 a become OFF. Moreover, an input signal Ia isinputted from the input terminal A, an input signal Ib is inputted fromeach of the input terminals B and E, and similarly, an input signal Icis inputted from each of the input terminals C and G. On this occasion,a sum and a carry of the input signals Ia, Ib, and Ic are outputtedrespectively as the output signals Sx and Sy from the output terminals Xand Y. Namely, the logic module 10 operates as a full adding circuit ofa combinational logic circuit.

[0087] Moreover, in FIG. 5, a logic low is applied from the inputterminal E to the two-input exclusive-NOR circuit 14 and a logic high isapplied from the input terminal G to the two-input exclusive-OR circuit19 so that the two-input exclusive-NOR circuit 14 and the two-inputexclusive-OR circuit 19 substantially operate as inverters, and clocksignals are inputted from the input terminals D and F to the switchingcircuits 11 a and 11 b , and 12 a and 12 b . On this occasion, the inputsignal Ia inputted from the input terminal A is delayed insynchronization with the clock signals and outputted as the outputsignal Sx from the output terminal X. In other words, the logic module10 operates as a delay circuit (D-type flip-flop) of a sequentialcircuit. Incidentally, when the logic module 10 is operated as the delaycircuit of the sequential circuit, input signals inputted from the inputterminals B and C are optional.

[0088] The cases where the logic module shown in FIG. 5 operates as afull adding circuit (full adder) and operates as a delay circuit (D-typeflip-flop) are explained above, but operations by the logic module shownin FIG. 5 are not limited to the aforementioned two operations. It isneedless to say that in the logic module in the second embodiment of thepresent invention, by inputting predetermined input signals from theinput terminals A to G, various kinds of combinational logic circuitsincluding a selector circuit which selects any one of inputted inputsignals and outputs it, for example, can be realized.

[0089]FIG. 6 to FIG. 8 are diagrams showing other examples of theconfiguration of the logic module in the second embodiment.

[0090] The logic module 10 shown in each of FIG. 6 to FIG. 8 and thelogic module 10 shown in FIG. 5 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configurations ofthe logic modules 10 shown in FIG. 6 to FIG. 8 and the configuration ofthe logic module 10 shown in FIG. 5 are different from each other. Thesignal for controlling the switching circuits 13 a and 13 b is theoutput signal of the inverter 16 in the logic module 10 shown in FIG. 6,but both the output signal of the two-input exclusive-NOR circuit 14 andthe output signal of the inverter 16 in the logic module 10 shown ineach of FIG. 7 and FIG. 8. Moreover, with the difference between thesignals for controlling the switching circuits 13 a and 13 b , logicvalues (a logic high, a logic low) at which the switching circuits 13 aand 13 b operate also differ according to supplied signals.

[0091] It should be mentioned that the operations of the logic modules10 shown in FIG. 6 to FIG. 8 are the same as that of the logic moduleshown in FIG. 5.

[0092] As explained above, according to the second embodiment, byconfiguring the logic module 10 as shown in each of FIG. 5 to FIG. 8,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0093] In this case, the two-input exclusive-NOR circuits 14 shown inFIG. 5 to FIG, 8 can be structured, for example, by circuits shown inFIG. 33A and FIG. 33B, and the two-input exclusive-OR circuits 19 can bestructured, for example, by circuits shown in FIG. 34A and FIG. 34B.FIG. 34A and FIG. 34B are diagrams each showing an example of thetwo-input exclusive-OR circuit. Incidentally, the configurations andoperations of the two-input exclusive-OR circuits shown in FIG. 34A andFIG. 34B will be described later.

[0094] By using such a circuit as shown in FIG. 33A or FIG. 33B, thetwo-input exclusive-NOR circuit 14 can be composed of four transistors,and by using such a circuit as shown in FIG. 34A or FIG. 34B, thetwo-input exclusive-OR circuit 19 can be composed of four transistors,whereby the number of transistors composing the logic module 10 can beeffectively decreased.

[0095] In the logic module 10 in the second embodiment shown in each ofFIG. 5 to FIG. 8, the number of transistors necessary to constitute thelogic module 10 is 18, and consequently a function almost equal to thatin the aforementioned conventional example can be realized by the numberof transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Third Embodiment

[0096] Next, regarding a logic module constituting a variable functioninformation processor according to the third embodiment of the presentinvention, its configuration and operation will be explained.

[0097]FIG. 9 is a diagram showing an example of the configuration of thelogic module in the third embodiment.

[0098] In FIG. 9, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither of them selectively becomes ON according to a signal Sd inputtedfrom an input terminal D to transmit the signal Sa or the output signalof the inverter 16 to a two-input exclusive-OR circuit 18 as one inputsignal. The other input signal of the two-input exclusive-OR circuit 18is a signal Se inputted from an input terminal E. An output signal ofthe two-input exclusive-OR circuit 18 is inputted as an input signal tothe inverter 16.

[0099] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the inverter 16. Theswitching circuits 12 a and 12 b are designed to selectively become ONaccording to a signal Sf inputted from an input terminal F to transmitthe output signal of the inverter 17 or the output signal of theinverter 16 to a two-input exclusive-NOR circuit 15 as one input signal.The other input signal of the two-input exclusive-NOR circuit 15 is asignal Sg inputted from an input terminal G. An output signal of thetwo-input exclusive-NOR circuit 15 is inputted to the inverter 17 as aninput signal.

[0100] Further, an output terminal of the two-input exclusive-NORcircuit 15 and an output terminal X of a logic module 10 are connectedto each other, and the output signal of the two-input exclusive-NORcircuit 15 is outputted as an output signal Sx of the logic module 10.Furthermore, the output signal of the inverter 16 is supplied toswitching circuits 13 a and 13 b respectively. The switching circuits 13a and 13 b are controlled by the output signal of the inverter 16 sothat a signal Sb inputted from an input terminal B or a signal Scinputted from an input terminal C is selectively transmitted to anoutput terminal Y. Thus, the signal Sb or Sc transmitted selectively isoutputted as an output signal Sy of the logic module 10 from the outputterminal Y.

[0101] In FIG. 9, a logic high is applied to the switching circuits 11 aand 11 b from the input terminal D and a logic low is applied to theswitching circuits 12 a and 12 b from the input terminal F so that theswitching circuits 11 a and 12 b become ON and that the switchingcircuits 11 b and 12 a become OFF. Moreover, an input signal Ia isinputted from the input terminal A, an input signal Ib is inputted fromeach of the input-terminals B and E, and similarly, an input signal Icis inputted from each of the input terminals C and G. On this occasion,a sum and a carry of the input signals Ia, Ib, and Ic are outputtedrespectively as the output signals Sx and Sy from the output terminals Xand Y. Namely, the logic module 10 operates as a full adding circuit ofa combinational logic circuit.

[0102] Moreover, in FIG. 9, a logic high is applied from the inputterminal E to the two-input exclusive-OR circuit 18 and a logic low isapplied from the input terminal G to the two-input exclusive-NOR circuit15 so that the two-input exclusive-OR circuit 18 and the two-inputexclusive-NOR circuit 15 substantially operate as inverters, and clocksignals are inputted from the input terminals D and F to the switchingcircuits 11 a and 11 b , and 12 a and 12 b . On this occasion, the inputsignal Ia inputted from the input terminal A is delayed insynchronization with the clock signals and outputted as the outputsignal Sx from the output terminal X. In other words, the logic module10 operates as a delay circuit (D-type flip-flop) of a sequentialcircuit. Incidentally, when the logic module 10 is operated as the delaycircuit of the sequential circuit, input signals inputted from the inputterminals B and C are optional.

[0103] The cases where the logic module shown in FIG. 9 operates as afull adding circuit (full adder) and operates as a delay circuit (D-typeflip-flop) are explained above, but operations by the logic module shownin FIG. 9 are not limited to the aforementioned two operations. It isneedless to say that in the logic module in the third embodiment of thepresent invention, by inputting predetermined input signals from theinput terminals A to G, various kinds of combinational logic circuitsincluding a selector circuit which selects any one of inputted inputsignals and outputs it, for example, can be realized.

[0104]FIG. 10 to FIG. 12 are diagrams showing other examples of theconfiguration of the logic module in the third embodiment.

[0105] The logic module 10 shown in each of FIG. 10 to FIG. 12 and thelogic module 10 shown in FIG. 9 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configuration of thelogic module 10 shown in each of FIG. 10 to FIG. 12 and theconfiguration of the logic module 10 shown in FIG. 9 are different fromeach other. The signal for controlling the switching circuits 13 a and13 b is the output signal of the two-input exclusive-OR circuit 18 inthe logic module 10 shown in FIG. 10, but both the output signal of thetwo-input exclusive-OR circuit 18 and the output signal of the inverter16 in the logic module 10 shown in each of FIG. 11 and FIG.12. Moreover,with the difference between the signals for controlling the switchingcircuits 13 a and 13 b , logic values (a logic high, a logic low) atwhich the switching circuits 13 a and 13 b operate also differ accordingto supplied signals.

[0106] It should be mentioned that the operations of the logic modules10 shown in FIG. 10 to FIG. 12 are the same as that of the logic moduleshown in FIG. 9.

[0107] As explained above, according to the third embodiment, byconfiguring the logic module 10 as shown in each of FIG. 9 to FIG. 12,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0108] In this case, the two-input exclusive-NOR circuits 15 shown inFIG. 9 to FIG. 12 can be structured, for example, by circuits shown inFIG. 33A and FIG. 33B, and the two-input exclusive-OR circuits 18 can bestructured, for example, by circuits shown in FIG. 34A and FIG. 34B.Thereby, it becomes possible that the two-input exclusive-NOR circuit 15and the two-input exclusive-OR circuit 18 are each composed of fourtransistors, whereby the number of transistors composing the logicmodule 10 can be effectively decreased.

[0109] In the logic module 10 in the third embodiment shown in each ofFIG. 9 to FIG. 12, the number of transistors necessary to constitute thelogic module 10 is 18, and consequently a function almost equal to thatin the aforementioned conventional example can be realized by the numberof transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Fourth Embodiment

[0110] Next, regarding a logic module constituting a variable functioninformation processor according to the fourth embodiment of the presentinvention, its configuration and operation will be explained.

[0111]FIG. 13 is a diagram showing an example of the configuration ofthe logic module in the fourth embodiment.

[0112] In FIG. 13, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither of them selectively becomes ON according to a signal Sd inputtedfrom an input terminal D to transmit the signal Sa or the output signalof the inverter 16 to a two-input exclusive-OR circuit 18 as one inputsignal. The other input signal of the two-input exclusive-OR circuit 18is a signal Se inputted from an input terminal E. An output signal ofthe two-input exclusive-OR circuit 18 is inputted to the inverter 16 asan input signal.

[0113] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the inverter 16. Theswitching circuits 12 a and 12 b are designed to selectively become ONaccording to a signal Sf inputted from an input terminal F to transmitthe output signal of the inverter 17 or the output signal of theinverter 16 to a two-input exclusive-OR circuit 19 as one input signal.The other input signal of the two-input exclusive-OR circuit 19 is asignal Sg inputted from an input terminal G. An output signal of thetwo-input exclusive-OR circuit 19 is inputted to the inverter 17 as aninput signal.

[0114] Further, an output terminal of the inverter 17 and an outputterminal X of a logic module 10 are connected to each other, and theoutput signal of the inverter 17 is outputted as an output signal Sx ofthe logic module 10. Furthermore, the output signal of the inverter 16is supplied to switching circuits 13 a and 13 b respectively. Theswitching circuits 13 a and 13 b are controlled by the output signal ofthe inverter 16 so that a signal Sb inputted from an input terminal B ora signal Sc inputted from an input terminal C is selectively transmittedto an output terminal Y. Thus, the signal Sb or Sc transmittedselectively is outputted as an output signal Sy of the logic module 10from the output terminal Y.

[0115] In FIG. 13, a logic high is applied to the switching circuits 11a and 11 b from the input terminal D and a logic low is applied to theswitching circuits 12 a and 12 b from the input terminal F so that theswitching circuits 11 a and 12 b become ON and that the switchingcircuits 11 b and 12 a become OFF. Moreover, an input signal Ia isinputted from the input terminal A, an input signal Ib is inputted fromeach of the input terminals B and E, and similarly, an input signal Icis inputted from each of the input terminals C and G. On this occasion,a sum and a carry of the input signals Ia, Ib, and Ic are outputtedrespectively as the output signals Sx and Sy from the output terminals Xand Y. Namely, the logic module 10 operates as a full adding circuit ofa combinational logic circuit.

[0116] Moreover, in FIG. 13, logic highs are applied from the inputterminals E and G to the two-input exclusive-OR circuits 18 and 19 sothat the two-input exclusive-OR circuits 18 and 19 substantially operateas inverters, and clock signals are inputted from the input terminals Dand F to the switching circuits 11 a and 11 b , and 12 a and 12 b . Onthis occasion, the input signal Ia inputted from the input terminal A isdelayed in synchronization with the clock signals and outputted as theoutput signal Sx from the output terminal X. In other words, the logicmodule 10 operates as a delay circuit (D-type flip-flop) of a sequentialcircuit. Incidentally, when the logic module 10 is operated as the delaycircuit of the sequential circuit, input signals inputted from the inputterminals B and C are optional.

[0117] The cases where the logic module shown in FIG. 13 operates as thefull adding circuit (full adder) and operates as the delay circuit(D-type flip-flop) are explained above, but operations by the logicmodule shown in FIG. 13 are not limited to the aforementioned twooperations. It is needless to say that in the logic module in the fourthembodiment of the present invention, by inputting predetermined inputsignals from the input terminals A to G, various kinds of combinationallogic circuits including a selector circuit which selects any one ofinputted input signals and outputs it, for example, can be realized.

[0118]FIG. 14 to FIG. 16 are diagrams showing other examples of theconfiguration of the logic module in the fourth embodiment.

[0119] The logic module 10 shown in each of FIG. 14 to FIG. 16 and thelogic module 10 shown in FIG. 13 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configuration of thelogic module 10 shown in each of FIG. 14 to FIG. 16 and theconfiguration of the logic module 10 shown in FIG. 13 are different fromeach other. The signal for controlling the switching circuits 13 a and13 b is the output signal of the two-input exclusive-OR circuit 18 inthe logic module 10 shown in FIG. 14, but both the output signal of thetwo-input exclusive-OR circuit 18 and the output signal of the inverter16 in the logic module 10 shown in each of FIG. 15 and FIG.16. Moreover,with the difference between the signals for controlling the switchingcircuits 13 a and 13 b , logic values (a logic high, a logic low) atwhich the switching circuits 13 a and 13 b operate also differ accordingto supplied signals.

[0120] It should be mentioned that the operations of the logic modules10 shown in FIG. 14 to FIG. 16 are the same as that of the logic moduleshown in FIG. 13.

[0121] As explained above, according to the fourth embodiment, byconfiguring the logic module 10 as shown in each of FIG. 13 to FIG. 16,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0122] In this case, the two-input exclusive-OR circuits 18 and 19 shownin FIG. 13 to FIG. 16 can be structured, for example, by circuits shownin FIG. 34A and FIG. 34B. Thereby, it becomes possible that thetwo-input exclusive-OR circuits 18 and 19 are each composed of fourtransistors, whereby the number of transistors composing the logicmodule 10 can be effectively decreased.

[0123] In the logic module 10 in the fourth embodiment shown in each ofFIG. 13 to FIG. 16, the number of transistors necessary to constitutethe logic module 10 is 18, and consequently a function almost equal tothat in the aforementioned conventional example can be realized by thenumber of transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Fifth Embodiment

[0124] Next, regarding a logic module constituting a variable functioninformation processor according to the fifth embodiment of the presentinvention, its configuration and operation will be explained.

[0125]FIG. 17 is a diagram showing an example of the configuration ofthe logic module in the fifth embodiment.

[0126] In FIG. 17, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither one of them selectively becomes ON according to a signal Sdinputted from an input terminal D to transmit the signal Sa or theoutput signal of the inverter 16 to a two-input exclusive-NOR circuit 14as one input signal. The other input signal of the two-inputexclusive-NOR circuit 14 is a signal Se inputted from an input terminalE. An output signal of the two-input exclusive-NOR circuit 14 isinputted to the inverter 16 as an input signal.

[0127] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the inverter 16. Theswitching circuits 12 a and 12 b are designed to selectively become ONaccording to a signal Sf inputted from an input terminal F to transmitthe output signal of the inverter 17 or the output signal of theinverter 16 to a two-input exclusive-NOR circuit 15 as one input signal.The other input signal of the two-input exclusive-NOR circuit 15 is asignal Sg inputted from an input terminal G. An output signal of thetwo-input exclusive-NOR circuit 15 is inputted to the inverter 17 as aninput signal.

[0128] Further, an output terminal of the inverter 17 and an outputterminal X of a logic module 10 are connected to each other, and theoutput signal of the inverter 17 is outputted as an output signal Sx ofthe logic module 10. Furthermore, the output signal of the two-inputexclusive-NOR circuit 14 is supplied to switching circuits 13 a and 13 brespectively. The switching-circuits 13 a and 13 b are-controlled by theoutput signal of the two-input exclusive-NOR circuit 14 so that a signalSb inputted from an input terminal B or a signal Sc inputted from aninput terminal C is selectively transmitted to an output terminal Y.Thus, the signal Sb or Sc transmitted selectively is outputted as anoutput signal Sy of the logic module 10 from the output terminal Y.

[0129] In FIG. 17, a logic high is applied to the switching circuits 11a and 11 b from the input terminal D and a logic low is applied to theswitching circuits 12 a and 12 b from the input terminal F so that theswitching circuits 11 a and 12 b become ON and that the switchingcircuits 11 b and 12 a become OFF. Moreover, an input signal Ia isinputted from the input terminal A, an input signal Ib is inputted fromeach of the input terminals B and E, and similarly, an input signal Icis inputted from each of the input terminals C and G. On this occasion,a sum and a carry of the input signals Ia, Ib, and Ic are outputtedrespectively as the output signals Sx and Sy from the output terminals Xand Y. Namely, the logic module 10 operates as a full adding circuit ofa combinational logic circuit.

[0130] Moreover, in FIG. 17, logic lows are applied to the two-inputexclusive-NOR circuits 14 and 15 from the input terminals E and Grespectively so that the two-input exclusive-NOR circuits 14 and 15substantially operate as inverters, and clock signals are inputted fromthe input terminals D and F to the switching circuits 11 a and 11 b ,and 12 a and 12 b . On this occasion, the input signal Ia inputted fromthe input terminal A is delayed in synchronization with the clocksignals and outputted as the output signal Sx from the output terminalX. In other words, the logic module 10 operates as a delay circuit(D-type flip-flop) of a sequential circuit. Incidentally, when the logicmodule 10 is operated as the delay circuit of the sequential circuit,input signals inputted from the input terminals B and C are optional.

[0131] The cases where the logic module shown in FIG. 17 operates as thefull adding circuit (full adder) and operates as the delay circuit(D-type flip-flop) are explained above, but operations by the logicmodule shown in FIG. 17 are not limited to the aforementioned twooperations. It is needless to say that in the logic module in the fifthembodiment of the present invention, by inputting predetermined inputsignals from the input terminals A to G, various kinds of combinationallogic circuits including a selector circuit which selects any one ofinputted input signals and outputs it, for example, can be realized.

[0132]FIG. 18 to FIG. 20 are diagrams showing other examples of theconfiguration of the logic module in the fifth embodiment.

[0133] The logic module 10 shown in each of FIG. 18 to FIG. 20 and thelogic module 10 shown in FIG. 17 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configuration of thelogic module 10 shown in each of FIG. 18 to FIG. 20 and theconfiguration of the logic module 10 shown in FIG. 17 are different fromeach other. The signal for controlling the switching circuits 13 a and13 b is the output signal of the inverter 16 in the logic module 10shown in FIG. 18, but both the output signal of the two-inputexclusive-NOR circuit 14 and the output signal of the inverter 16 in thelogic module 10 shown in each of FIG. 19 and FIG. 20. Moreover, with thedifference between the signals for controlling the switching circuits 13a and 13 b , logic values (a logic high, a logic low) at which theswitching circuits 13 a and 13 b operate also differ according tosupplied signals.

[0134] It should be mentioned that the operations of the logic modules10 shown in FIG. 18 to FIG. 20 are the same as that of the logic moduleshown in FIG. 17.

[0135] As explained above, according to the fifth embodiment, byconfiguring the logic module 10 as shown in each of FIG. 17 to FIG. 20,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0136] In this case, the two-input exclusive-NOR circuits 14 and 15shown in FIG. 17 to FIG. 20 can be structured, for example, by circuitsshown in FIG. 33A and FIG. 33B. Thereby, it becomes possible that thetwo-input exclusive-NOR circuits 14 and 15 are each composed of fourtransistors, whereby the number of transistors composing the logicmodule 10 can be effectively decreased.

[0137] In the logic module 10 in the fifth embodiment shown in each ofFIG. 17 to FIG. 20, the number of transistors necessary to constitutethe logic module 10 is 18, and consequently a function almost equal tothat in the aforementioned conventional example can be realized by thenumber of transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Sixth Embodiment

[0138] Next, regarding a logic module constituting a variable functioninformation processor according to the sixth embodiment of the presentinvention, its configuration and operation will be explained.

[0139]FIG. 21 is a diagram showing an example of the configuration ofthe logic module in the sixth embodiment.

[0140] In FIG. 21, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither of them selectively becomes ON according to a signal Sd inputtedfrom an input terminal D to transmit the signal Sa or the output signalof the inverter 16 to a two-input exclusive-NOR circuit 14 as one inputsignal. The other input signal of the two-input exclusive-NOR circuit 14is a signal Se inputted from an input terminal E. An output signal ofthe two-input exclusive-NOR circuit 14 is inputted to the inverter 16 asan input signal.

[0141] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the inverter 16. Theswitching circuits 12 a and 12 b are designed to selectively become ONaccording to a signal Sf inputted from an input terminal F to transmitthe output signal of the inverter 17 or the output signal of theinverter 16 to a two-input exclusive-OR circuit 19 as one input signal.The other input signal of the two-input exclusive-OR circuit 19 is asignal Sg inputted from an input terminal G. An output signal of thetwo-input exclusive-OR circuit 19 is inputted to the inverter 17 as aninput signal.

[0142] Further, an output terminal of the two-input exclusive-OR circuit19 and an output terminal X of a logic module 10 are-connected to eachother, and the output signal of the two-input exclusive-OR circuit 19 isoutputted as an output signal Sx of the logic module 10. Furthermore,the output signal of the two-input exclusive-NOR circuit 14 is suppliedto switching circuits 13 a and 13 b respectively. The switching circuits13 a and 13 b are controlled by the output signal of the two-inputexclusive-NOR circuit 14 so that a signal Sb inputted from an inputterminal B or a signal Sc inputted from an input terminal C isselectively transmitted to an output terminal Y. Thus, the signal Sb orSc transmitted selectively is outputted as an output signal Sy of thelogic module 10 from the output terminal Y.

[0143] In FIG. 21, a logic high is applied to the switching circuits 11a and 11 b from the input terminal D and a logic low is applied to theswitching circuits 12 a and 12 b from the input terminal F so that theswitching circuits 11 a and 12 b become ON and that the switchingcircuits 11 b and 12 a become OFF. Moreover, an input signal Ia isinputted from the input terminal A, an input signal Ib is inputted fromeach of the input terminals B and E, and similarly, an input signal Icis inputted from each of the input terminals C and G. On this occasion,a sum and a carry of the input signals Ia, Ib, and Ic are outputtedrespectively as the output signals Sx and Sy from the output terminals Xand Y. Namely, the logic module 10 operates as a full adding circuit ofa combinational logic circuit.

[0144] Moreover, in FIG. 21, a logic low is inputted to the two-inputexclusive-NOR circuit 14 from the input terminal E, and a logic high isapplied to the two-input exclusive-OR circuit 19 from the input terminalG so that the two-input exclusive-NOR circuit 14 and the two-inputexclusive-OR circuit 19 substantially operate as inverters, and clocksignals are inputted from the input terminals D and F to the switchingcircuits 11 a and 11 b , and 12 a and 12 b . On this occasion, the inputsignal Ia inputted from the input terminal A is delayed insynchronization with the clock signals and outputted as the outputsignal Sx from the output terminal X. In other words, the logic module10 operates as a delay circuit (D-type flip-flop) of a sequentialcircuit. Incidentally, when the logic module 10 is operated as the delaycircuit of the sequential circuit, input signals inputted from the inputterminals B and C are optional.

[0145] The cases where the logic module shown in FIG. 21 operates as thefull adding circuit (full adder) and operates as the delay circuit(D-type flip-flop) are explained above, but operations by the logicmodule shown in FIG. 21 are not limited to the aforementioned twooperations. It is needless to say that in the logic module in the sixthembodiment of the present invention, by inputting predetermined inputsignals from the input terminals A to G, various kinds of combinationallogic circuits including a selector circuit which selects any one ofinputted input signals and outputs it, for example, can be realized.

[0146]FIG. 22 to FIG. 24 are diagrams showing other examples of theconfiguration of the logic module in the sixth embodiment.

[0147] The logic module 10 shown in each of FIG. 22 to FIG. 24 and thelogic module 10 shown in FIG. 21 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configuration of thelogic module 10 shown in each of FIG. 22 to FIG. 24 and theconfiguration of the logic module 10 shown in FIG. 21 are different fromeach other. The signal for controlling the switching circuits 13 a and13 b is the output signal of the inverter 16 in the logic module 10shown in FIG. 22, but both the output signal of the two-inputexclusive-NOR circuit 14 and the output signal of the inverter 16 in thelogic module 10 shown in each of FIG. 23 and FIG.24. Moreover, with thedifference between the signals for controlling the switching circuits 13a and 13 b , logic values (a logic high, a logic low) at which theswitching circuits 13 a and 13 b operate also differ according tosupplied signals.

[0148] It should be mentioned that the operations of the logic modules10 shown in FIG. 22 to FIG. 24 are the same as that of the logic moduleshown in FIG. 21.

[0149] As explained above, according to the sixth embodiment, byconfiguring the logic module 10 as shown in each of FIG. 21 to FIG. 24,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0150] In this case, the two-input exclusive-NOR circuits 14 shown inFIG. 21 to FIG. 24 can be structured, for example, by circuits shown inFIG. 33A and FIG. 33B, and the two-input exclusive-OR circuits 19 can bestructured, for example, by circuits shown in FIG. 34A and FIG. 34B.Thereby, it becomes possible that the two-input exclusive-NOR circuit 14and the two-input exclusive-OR circuit 19 are each composed of fourtransistors, whereby the number of transistors composing the logicmodule 10 can be effectively decreased.

[0151] In the logic module 10 in the sixth embodiment shown in each ofFIG. 21 to FIG. 24, the number of transistors necessary to constitutethe logic module 10 is 18, and consequently a function almost equal tothat in the aforementioned conventional example can be realized by thenumber of transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Seventh Embodiment

[0152] Next, regarding a logic module constituting a variable functioninformation processor according to the seventh embodiment of the presentinvention, its configuration and operation will be explained.

[0153]FIG. 25 is a diagram showing an example of the configuration ofthe logic module in the seventh embodiment.

[0154] In FIG. 25, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither of them selectively becomes ON according to a signal Sd inputtedfrom an input terminal D to transmit the signal Sa or the output signalof the inverter 16 to a two-input exclusive-OR circuit 18 as one inputsignal. The other input signal of the two-input exclusive-OR circuit 18is a signal Se inputted from an input terminal E. An output signal ofthe two-input exclusive-OR circuit 18 is inputted to the inverter 16 asan input signal.

[0155] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the two-input exclusive-ORcircuit 18. The switching circuits 12 a and 12 b are designed toselectively become ON according to a signal Sf inputted from an inputterminal F to transmit the output signal of the inverter 17 or theoutput signal of the two-input exclusive-OR circuit 18 to a two-inputexclusive-NOR circuit 15 as one input signal. The other input signal ofthe two-input exclusive-NOR circuit 15 is a signal Sg inputted from aninput terminal G. An output signal of the two-input exclusive-NORcircuit 15 is inputted to the inverter 17 as an input signal.

[0156] Further, an output terminal of the inverter 17 and an outputterminal X of a logic module 10 are connected to each other, and theoutput signal of the inverter 17 is outputted as an output signal Sx ofthe logic module 10. Furthermore, the output signal of the inverter 16is supplied to switching circuits 13 a and 13 b respectively. Theswitching circuits 13 a and 13 b are controlled by the output signal ofthe inverter 16 so that a signal Sb inputted from an input terminal B ora signal Sc inputted from an input terminal C is selectively transmittedto an output terminal Y. Thus, the signal Sb or Sc transmittedselectively is outputted as an output signal Sy of the logic module 10from the output terminal Y.

[0157] In FIG. 25, a logic high is applied to the switching circuits 11a and 11 b from the input terminal D and a logic low is applied to theswitching circuits 12 a and 12 b from the input terminal F so that theswitching circuits 11 a and 12 b become ON and that the switchingcircuits 11 b and 12 a become OFF. Moreover, an input signal Ia isinputted from the input terminal A, an input signal Ib is inputted fromeach of the input terminals B and E, and similarly, an input signal Icis inputted from each of the input terminals C and G. On this occasion,a sum and a carry of the input signals Ia, Ib, and Ic are outputtedrespectively as the output signals Sx and Sy from the output terminals Xand Y. Namely, the logic module 10 operates as a full adding circuit ofa combinational logic circuit.

[0158] Moreover, in FIG. 25, a logic high is inputted to the two-inputexclusive-OR circuit 18 from the input terminal E, and a logic low isapplied to the two-input exclusive-NOR circuit 15 from the inputterminal G so that the two-input exclusive-OR circuit 18 and thetwo-input exclusive-NOR circuit 15 substantially operate as inverters,and clock signals are inputted from the input terminals D and F to theswitching circuits 11 a and 11 b , and 12 a and 12 b . On this occasion,the input signal Ia inputted from the input terminal A is delayed insynchronization with the clock signals and outputted as the outputsignal Sx from the output terminal X. In other words, the logic module10 operates as a delay circuit (D-type flip-flop) of a sequentialcircuit. Incidentally, when the logic module 10 is operated as the delaycircuit of the sequential circuit, input signals inputted from the inputterminals B and C are optional.

[0159] The cases where the logic module shown in FIG. 25 operates as thefull adding circuit (full adder) and operates as the delay circuit(D-type flip-flop) are explained above, but operations by the logicmodule shown in FIG. 25 are not limited to the aforementioned twooperations. It is needless to say that in the logic module in theseventh embodiment of the present invention, by inputting predeterminedinput signals from the input terminals A to G, various kinds ofcombinational logic circuits including a selector circuit which selectsany one of inputted input signals and outputs it, for example, can berealized.

[0160]FIG. 26 to FIG. 28 are diagrams showing other examples of theconfiguration of the logic module in the seventh embodiment.

[0161] The logic module 10 shown in each of FIG. 26 to FIG. 28 and thelogic module 10 shown in FIG. 25 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configuration of thelogic module 10 shown in each of FIG. 26 to FIG. 28 and theconfiguration of the logic module 10 shown in FIG. 25 are different fromeach other. The signal for controlling the switching circuits 13 a and13 b is the output signal of the two-input exclusive-OR circuit 18 inthe logic module 10 shown in FIG. 26, but both the output signal of thetwo-input exclusive-OR circuit 18 and the output signal of the inverter16 in the logic module 10 shown in each of FIG. 27 and FIG. 28.Moreover, with the difference between the signals for controlling theswitching circuits 13 a and 13 b , logic values (a logic high, a logiclow) at which the switching circuits 13 a and 13 b operate also differaccording to supplied signals.

[0162] It should be mentioned that the operations of the logic modules10 shown in FIG. 26 to FIG. 28 are the same as that of the logic moduleshown in FIG. 25.

[0163] As explained above, according to the seventh embodiment, byconfiguring the logic module 10 as shown in each of FIG. 25 to FIG. 28,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0164] In this case, the two-input exclusive-NOR circuits 15 shown inFIG. 25 to FIG. 28 can be structured, for example, by circuits shown inFIG. 33A and FIG. 33B, and the two-input exclusive-OR circuits 18 can bestructured, for example, by circuits shown in FIG. 34A and FIG. 34B.Thereby, it becomes possible that the two-input exclusive-NOR circuit 15and the two-input exclusive-OR circuit 18 are each composed of fourtransistors, whereby the number of transistors composing the logicmodule 10 can be effectively decreased.

[0165] In the logic module 10 in the seventh embodiment shown in each ofFIG. 25 to FIG. 28, the number of transistors necessary to constitutethe logic module 10 is 18, and consequently a function almost equal tothat in the aforementioned conventional example can be realized by thenumber of transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Eighth Embodiment

[0166] Next, regarding a logic module constituting a variable functioninformation processor according to the eighth embodiment of the presentinvention, its configuration and operation will be explained.

[0167]FIG. 29 is a diagram showing an example of the configuration ofthe logic module in the eighth embodiment.

[0168] In FIG. 29, a switching circuit 11 a selects whether or not tooutput a signal Sa inputted from an input terminal A, and a switchingcircuit 11 b selects whether or not to output an output signal of aninverter 16. The switching circuits 11 a and 11 b are designed such thateither of them selectively becomes ON according to a signal Sd inputtedfrom an input terminal D to transmit the signal Sa or the output signalof the inverter 16 to a two-input exclusive-OR circuit 18 as one inputsignal. The other input signal of the two-input exclusive-OR circuit 18is a signal Se inputted from an input terminal E. An output signal ofthe two-input exclusive-OR circuit 18 is inputted as an input signal tothe inverter 16.

[0169] A switching circuit 12 a selects whether or not to output anoutput signal of an inverter 17, and a switching circuit 12 b selectswhether or not to output the output signal of the two-input exclusive-ORcircuit 18. The switching circuits 12 a and 12 b are designed toselectively become ON according to a signal Sf inputted from an inputterminal F to transmit the output signal of the inverter 17 or theoutput signal of the two-input exclusive-OR circuit 18 to a two-inputexclusive-OR circuit 19 as one input signal. The other input signal ofthe two-input exclusive-OR circuit 19 is a signal Sg inputted from aninput terminal G. An output signal of the two-input exclusive-OR circuit19 is inputted as an input signal to the inverter 17.

[0170] Further, an output terminal of the two-input exclusive-OR circuit19 and an output terminal X of a logic module 10 are connected to eachother, and the output signal of the two-input exclusive-OR circuit 19 isoutputted as an output signal Sx of the logic module 10. Furthermore,the output signal of the inverter 16 is supplied to switching circuits13 a and 13 b respectively. The switching circuits 13 a and 13 b arecontrolled by the output signal of the inverter 16 so that a signal Sbinputted from an input terminal B or a signal Sc inputted from an inputterminal C is selectively transmitted to an output terminal Y. Thus, thesignal Sb or Sc transmitted selectively is outputted as an output signalSy of the logic module 10 from the output terminal Y.

[0171] In FIG. 29, a logic high is applied to the switching circuits 11a and 11 b from the input terminal D and a logic low is applied to theswitching circuits 12 a and 12 b from the input terminal F so that theswitching circuits 11 a and 12 b become ON and that the switchingcircuits 11 b and 12 a become OFF. Moreover, an input signal Ia isinputted from the input terminal A, an input signal Ib is inputted fromeach of the input terminals B and E, and similarly, an input signal Icis inputted from each of the input terminals C and G. On this occasion,a sum and a carry of the input signals Ia, Ib, and Ic are outputtedrespectively as the output signals Sx and Sy from the output terminals Xand Y. Namely, the logic module 10 operates as a full adding circuit ofa combinational logic circuit.

[0172] Moreover, in FIG. 29, logic highs are inputted to the two-inputexclusive-OR circuits 18 and 19 from the input terminals E and Grespectively so that the two-input exclusive-OR circuits 18 and 19substantially operate as inverters, and clock signals are inputted fromthe input terminals D and F to the switching circuits 11 a and 11 b ,and 12 a and 12 b . On this occasion, the input signal Ia inputted fromthe input terminal A is delayed in synchronization with the clocksignals and outputted as the output signal Sx from the output terminalX. In other words, the logic module 10 operates as a delay circuit(D-type flip-flop) of a sequential circuit. Incidentally, when the logicmodule 10 is operated as the delay circuit of the sequential circuit,input signals inputted from the input terminals B and C are optional.

[0173] The cases where the logic module shown in FIG. 29 operates as thefull adding circuit (full adder) and operates as the delay circuit(D-type flip-flop) are explained above, but operations by the logicmodule shown in FIG. 29 are not limited to the aforementioned twooperations. It is needless to say that in the logic module in the eighthembodiment of the present invention, by inputting predetermined inputsignals from the input terminals A to G, various kinds of combinationallogic circuits including a selector circuit which selects any one ofinputted input signals and outputs it, for example, can be realized.

[0174]FIG. 30 to FIG. 32 are diagrams showing other examples of theconfiguration of the logic module in the eighth embodiment.

[0175] The logic module 10 shown in each of FIG. 30 to FIG. 32 and thelogic module 10 shown in FIG. 29 are different in a signal forcontrolling the switching circuits 13 a and 13 b for selectivelytransmitting the signals Sb and Sc inputted respectively from the inputterminals B and C to the output terminal Y, and the configuration of thelogic module 10 shown in each of FIG. 30 to FIG. 32 and theconfiguration of the logic module 10 shown in FIG. 29 are different fromeach other. The signal for controlling the switching circuits 13 a and13 b is the output signal of the two-input exclusive-OR circuit 18 inthe logic module 10 shown in FIG. 30, but both the output signal of thetwo-input exclusive-OR circuit 18 and the output signal of the inverter16 in the logic module 10 shown in each of FIG. 31 and FIG. 32.Moreover, with the difference between the signals for controlling theswitching circuits 13 a and 13 b , logic values (a logic high, a logiclow) at which the switching circuits 13 a and 13 b operate also differaccording to supplied signals.

[0176] It should be mentioned that the operations of the logic modules10 shown in FIG. 30 to FIG. 32 are the same as that of the logic moduleshown in FIG. 29.

[0177] As explained above, according to the eighth embodiment, byconfiguring the logic module 10 as shown in each of FIG. 29 to FIG. 32,both the full adding circuit which is the combinational logic circuitand the delay circuit which is the sequential circuit can be realized bythe same logic module 10. Further, by using a common part of asemiconductor circuit element group constituting the full adding circuitand the delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 10 can be effectivelydecreased.

[0178] In this case, the two-input exclusive-OR circuits 18 and 19 shownin FIG. 29 to FIG. 32 can be structured, for example, by circuits shownin FIG. 34A and FIG. 34B. Thereby, it becomes possible that thetwo-input exclusive-OR circuits 18 and 19 are each composed of fourtransistors, whereby the number of transistors composing the logicmodule 10 can be effectively decreased.

[0179] In the logic module 10 in the eighth embodiment shown in each ofFIG. 29 to FIG. 32, the number of transistors necessary to constitutethe logic module 10 is 18, and consequently a function almost equal tothat in the aforementioned conventional example can be realized by thenumber of transistors not more than a half of 42 which is the number oftransistors necessary in the aforementioned conventional example.

Example of Configuration of Two-input Exclusive-NOR Circuit

[0180]FIG. 33A and FIG. 33B are diagrams each showing an example of theconfigurations of the two-input exclusive-NOR circuits 14 and 15 in theaforementioned first to eighth embodiments.

[0181] In FIG. 33A, either a switching circuit 21 a or 21 b in atwo-input exclusive-NOR circuit 20 selectively becomes ON according toan input signal I11 inputted from an input terminal IN11. Thereby, aninput signal I12 inputted from an input terminal IN12 or an invertedsignal of the input signal I12 obtained by an inverter 22 is outputtedas an output signal O1 of the two-input exclusive-NOR circuit 20 from anoutput terminal OUT1.

[0182] Moreover, in FIG. 33B, either a switching circuit 26 a or 26 b ina two-input exclusive-NOR circuit 25 selectively becomes ON according toan input signal I11 inputted from an input terminal IN11, and either aswitching circuit 27 a or 27 b selectively becomes ON according to aninput signal I12 inputted from an input terminal IN12. Thereby, at leasteither the input signal I11 or the input signal I12, or a logic high isoutputted as an output signal O1 of the two-input exclusive-NOR circuit25 from an output terminal OUT1.

[0183] In other words, in each of the circuits shown in FIG. 33A andFIG. 33B, when both the input signals I11 and I12, which arerespectively inputted from the input terminals IN11 and IN12, are at thesame level as a logic low or as a logic high, the logic high isoutputted as the output signal O1 from the output terminal OUT1, andwhen the input signal I11 and the input signal I12 are not at the samelevel, the logic low is outputted as the output signal O1 from theoutput signal OUT1, whereby it is known that the two-input exclusive-NORcircuits 20 and 25 each perform a two-input exclusive-NOR operationcorrectly.

Example of Configuration of Two-input Exclusive-OR Circuit

[0184]FIG. 34A and FIG. 34B are diagrams each showing an example of theconfigurations of the two-input exclusive-OR circuits 18 and 19 in theaforementioned first to eighth embodiments.

[0185] In FIG. 34A, either a switching circuit 31 a or 31 b in atwo-input exclusive-OR circuit 30 selectively becomes ON according to aninput signal I21 inputted from an input terminal IN21. Thereby, an inputsignal I22 inputted from an input terminal IN22 or an inverted signal ofthe input signal I22 obtained by an inverter 32 is outputted as anoutput signal O2 of the two-input exclusive-OR circuit 30 from an outputterminal OUT2.

[0186] Moreover, in FIG. 34B, either a switching circuit 36 a or 3 b ina two-input exclusive-OR circuit 35 selectively becomes ON according toan input signal I21 inputted from an input terminal IN21, and either aswitching circuit 37 a or 37 b selectively becomes ON according to aninput signal I22 inputted from an input terminal IN22. Thereby, at leasteither the input signal I21 or the input signal I22, or a logic low isoutputted as an output signal O2 of the two-input exclusive-OR circuit35 from an output terminal OUT2.

[0187] In other words, in each of the circuits shown in FIG. 34A andFIG. 34B, when both the input signals I21 and I22, which arerespectively inputted from the input terminals IN21 and IN22, are at thesame level as a logic low or as a logic high, the logic low is outputtedas the output signal O2 from the output terminal OUT2, and when theinput signal I21 and the input signal I22 are not at the same level, thelogic high is outputted as the output signal O2 from the output signalOUT2, whereby it is known that the two-input exclusive-OR circuits 30and 35 each perform a two-input exclusive-OR operation correctly.

[0188] Through the use of such two-input exclusive-NOR circuits andtwo-input exclusive-OR circuits as described above, it becomes possiblethat a two-input exclusive-NOR circuit and a two-input exclusive-ORcircuit, each of which generally requires ten or more transistors, areeach composed of four transistors, whereby the number of transistorscomposing a logic module can be effectively decreased.

Ninth Embodiment

[0189] Next, regarding a logic module constituting a variable functioninformation processor according to the ninth embodiment of the presentinvention, its configuration and operation will be explained.

[0190]FIG. 35 is a diagram showing an example of the configuration ofthe logic module in the ninth embodiment.

[0191] In the ninth embodiment, as shown in FIG. 35, an output terminalof a two-input exclusive-OR circuit 41 and input terminals C and G in alogic module 10 are connected, and the two-input exclusive-OR circuit 41and the logic module 10 together are defined as a new logic module 40.Incidentally, the above logic module 10 is the logic module 10 in eachof the aforementioned first to eighth embodiments. Moreover, as shown inFIG. 35, input terminals of the new logic module 40 are represented byA, B, D, E, F, C1, and C2, and output terminals of the new logic module40 are represented by X and Y.

[0192] In FIG. 35, a logic high is applied to switching circuits 11 aand 11 b from the input terminal D and a logic low is applied toswitching circuits 12 a and 12 b from the input terminal F such that theswitching circuits 11 a and 12 b in the logic module 10 become ON andthat switching circuits 11 b and 12 a therein become OFF. Further, aninput signal Ia is inputted from the input terminal A, an input signalIb is inputted from each of the input terminals B and E, and similarly,an input signal Ic1 is inputted from the input terminal C1.

[0193] When the input signals are inputted respectively from the inputterminals A, B, D, E, F, and C1 as stated above and a logic low isinputted from the input terminal C2, a sum and a carry of the inputsignals Ia, Ib, and Ic are outputted as output signals Sx and Sy fromthe output terminals X and Y respectively. Namely, the logic module 40operates as an adding circuit for performing an addition operationrepresented by an expression (Ia+Ib+Ic).

[0194] Meanwhile, when the input signals-are inputted respectively fromthe input terminals A, B, D, E, F, and C1 as stated above and a logichigh is inputted from the input terminal C2, a sum and a carry of theinput signals Ia and Ib, and an inverted signal of the input signal Icare outputted as the output signals Sx and Sy from the output terminalsX and Y respectively. Namely, the logic module 40 operates as asubtracting circuit for performing a subtraction operation representedby an expression (Ia+Ib−Ic).

[0195] Furthermore, in FIG. 35, predetermined signals are applied to atwo-input exclusive-NOR circuit and a two-input exclusive-OR circuitused in the logic module 10 from the input terminals E, C1, and C2 sothat the two-input exclusive-NOR circuit and the two-input exclusive-ORcircuit substantially operate as inverters, and clock signals areinputted from the input terminals D and F to the switching circuits 11 aand 11 b , and 12 a and 12 b in the logic module 10. On this occasion,the input signal Ia inputted from the input terminal A is delayed insynchronization with the clock signals and outputted as the outputsignal Sx from the output terminal X. In other words, the new logicmodule 40 operates as a delay circuit (D-type flip-flop) of a sequentialcircuit. Incidentally, when the logic module 40 is operated as the delaycircuit of the sequential circuit, an input signal inputted from theinput terminal B is optional.

[0196] The cases where the logic module 40 shown in FIG. 35 operates asthe adding circuit (adder), operates as the subtracting circuit(subtracter), and operates as the delay circuit (D-type flip-flop) areexplained above, but operations by the logic module 40 shown in FIG. 35are not limited to the aforementioned three operations. It is needlessto say that in the logic module in the ninth embodiment of the presentinvention, by inputting predetermined input signals from the inputterminals A, B, D, E, F, C1, and C2, various kinds of combinationallogic circuits including a selector circuit which selects any one ofinputted input signals and outputs it, for example, can be realized.

[0197] As explained above, according to the ninth embodiment, byconfiguring the logic module 40 as shown in FIG. 35, both theadding/subtracting circuit which is the combinational logic circuit andthe delay circuit which is the sequential circuit can be realized by thesame logic module 40. Further, by using a common part of a semiconductorcircuit element group constituting the adding/subtracting circuit andthe delay circuit respectively for both the circuits, the number oftransistors constituting the logic module 40 can be effectivelydecreased.

Tenth Embodiment

[0198] Next, regarding a logic module constituting a variable functioninformation processor according to the tenth embodiment of the presentinvention, its configuration and operation will be explained.

[0199]FIG. 36 is a diagram showing an example of the configuration ofthe logic module in the tenth embodiment.

[0200] In the tenth embodiment, as shown in FIG. 36, an output terminalY of a logic module 10 a which is one of the logic modules 10 in theaforementioned first to eighth embodiments and input terminals C and Gof a logic module 10 b which is another of the logic modules 10 areconnected, and the logic module 10 a and the logic module 10 b togetherare defined as a new logic module 50. Moreover, as shown in FIG. 36,input terminals of the new logic module 50 are represented by A1, B1,D1, E1, A0, B0, C0, D0, E0, F0, and G0, and output terminals of the newlogic module 50 are represented by X0, X1, and Y1.

[0201] In FIG. 36, logic highs are applied to switching circuits 11 aand 11 b in the logic modules 10 a and 10 b from the input terminals D0and D1 respectively and logic lows are applied to switching circuits 12a and 12 b in the logic modules 10 a and 10 b from the input terminalsF0 and F1 respectively such that the switching circuits 11 a and 12 b inthe logic modules 10 a and 10 b become ON and the switching circuits 11b and 12 a therein become OFF. Further, input signals Ia0 and Ia1 areinputted from the input terminals A0 and Al respectively, an inputsignal Ib0 is inputted from each of the input terminals B0 and E0, aninput signal Ib1 is inputted from each of the input terminals BT and E1,and similarly, a logic low is inputted from each of the input terminalsC0 and G0. On this occasion, an operation result corresponding to thesum of an input signal AI {Ia1, Ia0} and an input signal BI {Ib1, Ib0}each of two bits is outputted to an output signal XO {Sy1, Sx1, Xx0} ofthree bits composed of output signals Sy1, Sx1, and Sx0 outputted fromthe output terminals Y1, X1, and X0 respectively, and the logic module50 operates as a 2-bit adding circuit for performing a 2-bit additionoperation shown by an expression (XO{Sy1, Sx1, Sx0}=AI{Ia1, Ia0}+{Ib1,Ib0}).

[0202] Furthermore, in FIG. 36, predetermined signals are applied to atwo-input exclusive-NOR circuit and a two-input exclusive-OR circuitused in the logic modules 10 a and 10 b from the input terminals E1, B0,C0, E0, and G0 so that the two-input exclusive-NOR circuit and thetwo-input exclusive-OR circuit substantially operate as inverters, andclock signals are inputted from the input terminals D0, D1, F0, and F1to the switching circuits 11 a , 11 b , 12 a , and 12 b in the logicmodules 10 a and 10 b . On this occasion, the input signals Ia0 and Ia1inputted from the input terminals A0 and A1 respectively are delayed insynchronization with the clock signals and outputted as the outputsignals Sx0 and Sx1 from the output terminals X0 and X1 respectively. Inother words, the new logic module 50 operates as a parallel 2-bit delaycircuit (D-type flip-flop).

[0203] The cases where the logic module 50 shown in FIG. 36 operates asthe 2-bit adding circuit and operates as the parallel 2-bit delaycircuit (D-type flip-flop) are explained above, but operations by thelogic module 50 shown in FIG. 36 are not limited to the aforementionedtwo operations. It is needless to say that in the logic module in thetenth embodiment of the present invention, by inputting predeterminedinput signals from the input terminals A1, B1, D1, E1, F1, and A0 to G0,various kinds of combinational logic circuits including a selectorcircuit which selects any one of inputted input signals and outputs it,for example, can be realized.

[0204] As explained above, according to the tenth embodiment, byconfiguring the logic module 50 as shown in FIG. 36, both the 2-bitadding circuit which is the combinational logic circuit and the parallel2-bit delay circuit which is the sequential circuit can be realized bythe same logic module 50. Further, by using a common part of asemiconductor circuit element group constituting the 2-bit addingcircuit and the parallel 2 bit delay circuit respectively for both thecircuits, the number of transistors constituting the logic module 50 canbe effectively decreased.

Eleventh Embodiment

[0205] Next, regarding a variable function information processoraccording to the eleventh embodiment of the present invention, itsconfiguration and operation will be explained.

[0206]FIG. 37 is a diagram showing an example of the configuration ofthe variable function information processor in the eleventh embodiment.

[0207] A variable function information processor 60 according to theeleventh embodiment is a variable function information processorrealized by arranging a plurality of one kind or several kinds of logicmodules explained in the aforementioned first to tenth embodiments(shown by logic modules 61 in the diagram) and connecting the pluralityof logic modules 61 to one other.

[0208] The variable function information processor 60 is composed of theplurality of logic modules 61 each having a function of serving both asa combinational logic circuit and as a sequential circuit bypredetermined signals, and hence by using the combinational logiccircuits and the sequential circuits which the logic modules 61 canprovide, the variable function information processor 60 operates as aninformation processor which performs various kinds of desiredinformation processing.

[0209] Moreover, the logic module 61 is a logic module which can use acommon part of a semiconductor circuit element group constituting thecombinational logic circuit and the sequential circuit respectively forboth the circuits to thereby effectively decrease the number oftransistors constituting the logic module 61, whereby the variablefunction information processor 60 the resources of which are effectivelyexploited is realized by a plurality of logic modules 61.

[0210] As explained above, according to the eleventh embodiment, therecan be provided the variable function information processor 60 which, inorder to integrate logic modules constituting the variable functioninformation processor as many as possible (at the highest possibledegree of integration), uses the logic modules 61 the resources of eachof which are effectively exploited by realizing both the combinationallogic circuit and the sequential circuit by the same logic module,whereby the number of transistors is further decreased.

[0211] It should be mentioned that terms “apply”, “transmit”, and“connect” described in this specification indicate a state of beingelectrically connected, including a case where a different element isinserted in its electrically connected path.

[0212] Moreover, it is easily understood from the aforementionedexplanation that the logic module constituting the variable functioninformation processor in each of the aforementioned first to tenthembodiment can realize an equivalent function by changing anexclusive-NOR circuit to an exclusive-OR circuit and according to thischange, changing a way of operating a switching circuit and a way ofapplying a signal, and by changing the configuration of the switchingcircuit, for example, through the use of a switching logic circuit suchas a multiplexer in place of a transistor switch and according to thischange, changing a way of applying a signal, and hence please note thatthe scope of the claims herein embraces all such changes included in thescope of the present invention.

[0213] It is needless to say that the logic module constituting thevariable function information processor in each of the aforementionedfirst to tenth embodiments may be used as one circuit elementconstituting an information processing unit such as a processor, may beused as a master slice such as a gate array, may be used as a basicmodule such as an FPGA, or may used for other various semiconductordevices.

Industrial Applicability

[0214] As described above, according to the present invention, thenumber of transistors used in a logic module constituting a variablefunction information processor can be further decreased, and by usingthe logic module, a variable function information processor in whichmore logic modules are integrated can be provided. Moreover, both acombinational logic circuit and a sequential circuit can be realized bythe same logic module, whereby the resources of the variable functioninformation processor can be effectively exploited.

What is claimed is:
 1. A variable function information processor,comprising: at least one basic circuit block composed of a two-inputarithmetic circuit structured by a two-input exclusive-NOR circuit or atwo-input exclusive-OR circuit, to which a first signal is inputted asone input signal from a first input terminal, an inverter for invertingan output signal of the two-input arithmetic circuit, a switchingcircuit for transmitting an output signal of the inverter or a secondsignal inputted from a second input terminal as the other input signalto the two-input arithmetic circuit in accordance with a third signalinputted from a third input terminal, and an output terminal capable ofoutputting at least either the output signal of the two-input arithmeticcircuit or the output signal of the inverter; an input terminal groupincluding the first to third input terminals; an output terminal groupincluding the output terminal; and a semiconductor arithmetic circuitelectrically connected to said input terminal group, said outputterminal group, and said basic circuit block, wherein a function ofserving both as a combinational logic circuit for performing a logicaloperation of the input signals and as a sequential circuit forperforming a sequential operation of the input signal according to theinput signals inputted from said input terminal group is provided, andthrough the use of said basic circuit block, in a semiconductor circuitelement group for constituting the combinational logic circuit and thesequential circuit, a common part of the combinational logic circuit andthe sequential circuit is used for both the circuits.
 2. The variablefunction information processor according to claim 1, wherein saidsemiconductor arithmetic circuit includes an output switching circuitfor selectively outputting any of the input signals inputted from saidinput terminal group.
 3. The variable function information processoraccording to claim 1, wherein a first and a second basic circuit blockare provided, wherein the first basic circuit block includes: a firsttwo-input arithmetic circuit structured by a first two-inputexclusive-NOR circuit or a first two-input exclusive-OR circuit, towhich a first signal is inputted as one input signal from a first inputterminal; a first inverter for inverting an output signal of the firsttwo-input arithmetic circuit; and a first switching circuit fortransmitting an output signal of the first inverter or a second signalinputted from a second input terminal as the other input signal to thefirst two-input arithmetic circuit in accordance with a third signalinputted from a third input terminal, the first basic circuit blockoutputting the output signal of the first two-input arithmetic circuitor the output signal of the first inverter as an output signal ofthe-first basic circuit block, wherein the second basic circuit blockincludes: a second two-input arithmetic circuit structured by a secondtwo-input exclusive-NOR circuit or a second two-input exclusive-ORcircuit, to which a fourth signal is inputted as one input signal from afourth input terminal; a second inverter for inverting an output signalof the second two-input arithmetic circuit; and a second switchingcircuit for transmitting an output signal of the second inverter or theoutput signal of the first basic circuit block as the other input signalto the second two-input arithmetic circuit in accordance with a fifthsignal inputted from a fifth input terminal, the second basic circuitblock outputting the output signal of the second two-input arithmeticcircuit or the output signal of the second inverter via a first externaloutput terminal, wherein said semiconductor arithmetic circuit transmitsa sixth signal inputted from a sixth input terminal or a seventh signalinputted from a seventh input terminal to a second external outputterminal in accordance with at least either the output signal of thefirst two-input arithmetic circuit or the output signal of the firstinverter, and wherein a function of serving both as a combinationallogic circuit for performing a full addition operation of the inputsignals and outputting a result of the operation and as a sequentialcircuit for temporarily holding the input signal to delay the inputsignal and outputting it according to the input signals inputted fromthe first to seventh input terminals is provided, and in a semiconductorcircuit element group for constituting the combinational logic circuitand the sequential circuit, a common part of the combinational logiccircuit and the sequential circuit is used for both the circuits.
 4. Thevariable function information processor according to claim 1, wherein afirst and a second basic circuit block are provided, wherein the firstbasic circuit block includes: a first two-input exclusive-NOR circuit,to which a first signal is inputted as one input signal from a firstinput terminal; a first inverter for inverting an output signal of thefirst two-input exclusive-NOR circuit; and a first switching circuit fortransmitting an output signal of the first inverter or a second signalinputted from a second input terminal as the other input signal to thefirst two-input exclusive-NOR circuit in accordance with a third signalinputted from a third input terminal, wherein the second basic circuitblock includes: a second two-input exclusive-NOR circuit, to which afourth signal is inputted as one input signal from a fourth inputterminal, for outputting an output signal via a first external outputterminal; a second inverter for inverting the output signal of thesecond two-input exclusive-NOR circuit; and a second switching circuitfor transmitting an output signal of the second inverter or the outputsignal of the first two-input exclusive-NOR circuit as the other inputsignal to the second two-input exclusive-NOR circuit in accordance witha fifth signal inputted from a fifth input terminal, wherein saidsemiconductor arithmetic circuit transmits a sixth signal inputted froma sixth input terminal or a seventh signal inputted from a seventh inputterminal to a second external output terminal in accordance with atleast either the output signal of the first two-input exclusive-NORcircuit or the output signal of the first inverter, and wherein afunction of serving both as a combinational logic circuit for performinga full addition operation of the input signals and outputting a resultof the operation and as a sequential circuit for temporarily holding theinput signal to delay the input signal and outputting it according tothe input signals inputted from the first to seventh input terminals isprovided, and in a semiconductor circuit element group for constitutingthe combinational logic circuit and the sequential circuit, a commonpart of the combinational logic circuit and the sequential circuit isused for both the circuits.
 5. The variable function informationprocessor according to claim 1, wherein a first and a second basiccircuit block are provided, wherein the first basic circuit blockincludes: a two-input exclusive-NOR circuit, to which a first signal isinputted as one input signal from a first input terminal; a firstinverter for inverting an output signal of the two-input exclusive-NORcircuit; and a first switching circuit for transmitting an output signalof the first inverter or a second signal inputted from a second inputterminal as the other input signal to the two-input exclusive-NORcircuit in accordance with a third signal inputted from a third inputterminal, wherein the second basic circuit block includes: a two-inputexclusive-OR circuit, to which a fourth signal is inputted as one inputsignal from a fourth input terminal; a second inverter for inverting anoutput signal of the two-input exclusive-OR circuit and outputting anoutput signal via a first external output terminal; and a secondswitching circuit for transmitting the output signal of the secondinverter or the output signal of the two-input exclusive-NOR circuit asthe other input signal to the two-input exclusive-OR circuit inaccordance with a fifth signal inputted from a fifth input terminal,wherein said semiconductor arithmetic circuit transmits a sixth signalinputted from a sixth input terminal or a seventh signal inputted from aseventh input terminal to a second external output terminal inaccordance with at least either the output signal of the two-inputexclusive-NOR circuit or the output signal of the first inverter, andwherein a function of serving both as a combinational logic circuit forperforming a full addition operation of the input signals and outputtinga result of the operation and as a sequential circuit for temporarilyholding the input signal to delay the input signal and outputting itaccording to the input signals inputted from the first to seventh inputterminals is provided, and in a semiconductor circuit element group forconstituting the combinational logic circuit and the sequential circuit,a common part of the combinational logic circuit and the sequentialcircuit is used for both the circuits.
 6. The variable functioninformation processor according to claim 1, wherein a first and a secondbasic circuit block are provided, wherein the first basic circuit blockincludes: a two-input exclusive-OR circuit, to which a first signal isinputted as one input signal from a first input terminal; a firstinverter for inverting an output signal of the two-input exclusive-ORcircuit; and a first switching circuit for transmitting an output signalof the first inverter or a second signal inputted from a second inputterminal as the other input signal to the two-input exclusive-OR circuitin accordance with a third signal inputted from a third input terminal,wherein the second basic circuit block includes: a two-inputexclusive-NOR circuit, to which a fourth signal is inputted as one inputsignal from a fourth input terminal, for outputting an output signal viaa first external output terminal; a second inverter for inverting theoutput signal of the two-input exclusive-NOR circuit; and a secondswitching circuit for transmitting an output signal of the secondinverter or the output signal of the first inverter as the other inputsignal to the two-input exclusive-NOR circuit in accordance with a fifthsignal inputted from a fifth input terminal, wherein said semiconductorarithmetic circuit transmits a sixth signal inputted from a sixth inputterminal or a seventh signal inputted from a seventh input terminal to asecond external output terminal in accordance with at least either theoutput signal of the two-input exclusive-OR circuit or the output signalof the first inverter, and wherein a function of serving both as acombinational logic circuit for performing a full addition operation ofthe input signals and outputting a result of the operation and as asequential circuit for temporarily holding the input signal to delay theinput signal and outputting it according to the input signals inputtedfrom the first to seventh input terminals is provided, and in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.
 7. The variable function information processor accordingto claim 1, wherein a first and a second basic circuit block areprovided, wherein the first basic circuit block includes: a firsttwo-input exclusive-OR circuit, to which a first signal is inputted asone input signal from a first input terminal; a first inverter forinverting an output signal of the first two-input exclusive-OR circuit;and a first switching circuit for transmitting an output signal of thefirst inverter or a second signal inputted from a second input terminalas the other input signal to the first two-input exclusive-OR circuit inaccordance with a third signal inputted from a third input terminal,wherein the second basic circuit block includes: a second two-inputexclusive-OR circuit, to which a fourth signal is inputted as one inputsignal from a fourth input terminal; a second inverter for inverting anoutput signal of the second two-input exclusive-OR circuit andoutputting an output signal via a first external output terminal; and asecond switching circuit for transmitting the output signal of thesecond inverter or the output signal of the first inverter as the otherinput signal to the second two-input exclusive-OR circuit in accordancewith a fifth signal inputted from a fifth input terminal, wherein saidsemiconductor arithmetic circuit transmits a sixth signal inputted froma sixth input terminal or a seventh signal inputted from a seventh inputterminal to a second external output terminal in accordance with atleast either the output signal of the first two-input exclusive-ORcircuit or the output signal of the first inverter, and wherein afunction of serving both as a combinational logic circuit for performinga full addition operation of the input signals and outputting a resultof the operation and as a sequential circuit for temporarily holding theinput signal to delay the input signal and outputting it according tothe input signals inputted from the first to seventh input terminals isprovided, and in a semiconductor circuit element group for constitutingthe combinational logic circuit and the sequential circuit, a commonpart of the combinational logic circuit and the sequential circuit isused for both the circuits.
 8. The variable function informationprocessor according to claim 1, wherein a first and a second basiccircuit block are provided, wherein the first basic circuit blockincludes: a first two-input exclusive-NOR circuit, to which a firstsignal is inputted as one input signal from a first input terminal; afirst inverter for inverting an output signal of the first two-inputexclusive-NOR circuit; and a first switching circuit for transmitting anoutput signal of the first inverter or a second signal inputted from asecond input terminal as the other input signal to the first two-inputexclusive-NOR circuit in accordance with a third signal inputted from athird input terminal, wherein the second basic circuit block includes: asecond two-input exclusive-NOR circuit, to which a fourth signal isinputted as one input signal from a fourth input terminal; a secondinverter for inverting an output signal of the two-input exclusive-NORcircuit and outputting an output signal via a first external outputterminal; and a second switching circuit for transmitting the outputsignal of the second inverter or the output signal of the first inverteras the other input signal to the second two-input exclusive-NOR circuitin accordance with a fifth signal inputted from a fifth input terminal,wherein said semiconductor arithmetic circuit transmits a sixth signalinputted from a sixth input terminal or a seventh signal inputted from aseventh input terminal to a second external output terminal inaccordance with at least either the output signal of the first two-inputexclusive-NOR circuit or the output signal of the first inverter, andwherein a function of serving both as a combinational logic circuit forperforming a full addition operation of the input signals and outputtinga result of the operation and as a sequential circuit for temporarilyholding the input signal to delay the input signal and outputting itaccording to the input signals inputted from the first to seventh inputterminals is provided, and in a semiconductor circuit element group forconstituting the combinational logic circuit and the sequential circuit,a common part of the combinational logic circuit and the sequentialcircuit is used for both the circuits.
 9. The variable functioninformation processor according to claim 1, wherein a first and a secondbasic circuit block are provided, wherein the first basic circuit blockincludes: a two-input exclusive-NOR circuit, to which a first signal isinputted as one input signal from a first input terminal; a firstinverter for inverting an output signal of the two-input exclusive-NORcircuit; and a first switching circuit for transmitting an output signalof the first inverter or a second signal inputted from a second inputterminal as the other input signal to the two-input exclusive-NORcircuit in accordance with a third signal inputted from a third inputterminal, wherein the second basic circuit block includes: a two-inputexclusive-OR circuit, to which a fourth signal is inputted as one inputsignal from a fourth input terminal and outputting an output signal viaa first external output terminal; a second inverter for inverting theoutput signal of the two-input exclusive-OR circuit; and a secondswitching circuit for transmitting an output signal of the secondinverter or the output signal of the first inverter as the other inputsignal to the two-input exclusive-OR circuit in accordance with a fifthsignal inputted from a fifth input terminal, wherein said semiconductorarithmetic circuit transmits a sixth signal inputted from a sixth inputterminal or a seventh signal inputted from a seventh input terminal to asecond external output terminal in accordance with at least either theoutput signal of the two-input exclusive-NOR circuit or the outputsignal of the first inverter, and wherein a function of serving both asa combinational logic circuit for performing a full addition operationof the input signals and outputting a result of the operation and as asequential circuit for temporarily holding the input signal to delay theinput signal and outputting it according to the input signals inputtedfrom the first to seventh input terminals is provided, and in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.
 10. The variable function information processor accordingto claim 1, wherein a first and a second basic circuit block areprovided, wherein the first basic circuit block includes: a two-inputexclusive-OR circuit, to which a first signal is inputted as one inputsignal from a first input terminal; a first inverter for inverting anoutput signal of the two-input exclusive-OR circuit; and a firstswitching circuit for transmitting an output signal of the firstinverter or a second signal inputted from a second input-terminal as theother input signal to the two-input exclusive-OR circuit in accordancewith a third signal inputted from a third input terminal, wherein thesecond basic circuit block includes: a two-input exclusive-NOR circuit,to which a fourth signal is inputted as one input signal from a fourthinput terminal; a second inverter for inverting an output signal of thetwo-input exclusive-NOR circuit and outputting an output signal via afirst external output terminal; and a second switching circuit fortransmitting the output signal of the second inverter or the outputsignal of the two-input exclusive-OR circuit as the other input signalto the second two-input exclusive-NOR circuit in accordance with a fifthsignal inputted from a fifth input terminal, wherein said semiconductorarithmetic circuit transmits a sixth signal inputted from a sixth inputterminal or a seventh signal inputted from a seventh input terminal to asecond external output terminal in accordance with at least either theoutput signal of the two-input exclusive-OR circuit or the output signalof the first inverter, and wherein a function of serving both as acombinational logic circuit for performing a full addition operation ofthe input signals and outputting a result of the operation and as asequential circuit for temporarily holding the input signal to delay theinput signal and outputting it according to the input signals inputtedfrom the first to seventh input terminals is provided, and in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.
 11. The variable function information processor accordingto claim 1, wherein a first and a second basic circuit block areprovided, wherein the first basic circuit block includes: a firsttwo-input exclusive-OR circuit, to which a first signal is inputted asone input signal from a first input terminal; a first inverter forinverting an output signal of the first two-input exclusive-OR circuit;and a first switching circuit for transmitting an output signal of thefirst inverter or a second signal inputted from a second input terminalas the other input signal to the first two-input exclusive-OR circuit inaccordance with a third signal inputted from a third input terminal,wherein the second basic circuit block includes: a second two-inputexclusive-OR circuit, to which a fourth signal is inputted as one inputsignal from a fourth input terminal, for outputting an output signal viaa first external output terminal; a second inverter for inverting theoutput signal of the second two-input exclusive-OR circuit; and a secondswitching circuit for transmitting an output signal of the secondinverter or the output signal of the first two-input exclusive-ORcircuit as the other input signal to the second two-input exclusive-ORcircuit in accordance with a fifth signal inputted from a fifth inputterminal, wherein said semiconductor arithmetic circuit transmits asixth signal inputted from a sixth input terminal or a seventh signalinputted from a seventh input terminal to a second external outputterminal in accordance with at least either the output signal of thefirst two-input exclusive-OR circuit or the output signal of the firstinverter, and wherein a function of serving both as a combinationallogic circuit for performing a full addition operation of the inputsignals and outputting a result of the operation and as a sequentialcircuit for temporarily holding the input signal to delay the inputsignal and outputting it according to the input signals inputted fromthe first to seventh input terminals is provided, and in a semiconductorcircuit element group for constituting the combinational logic circuitand the sequential circuit, a common part of the combinational logiccircuit and the sequential circuit is used for both the circuits. 12.The variable function information processor according to claim 3,further comprising: a third two-input arithmetic circuit structured by athird two-input exclusive-NOR circuit or a third two-input exclusive-ORcircuit, whose output terminal is electrically connected to at least oneof the first to seventh input terminals, wherein a function of servingboth as a combinational logic circuit for performing an additionoperation or a subtraction operation of a set of the input signals andoutputting a result of the operation and as a sequential circuit fortemporarily holding the input signal to delay the input signal andoutputting it according to input signals inputted from input terminalsfor inputting input signals to the third two-input arithmetic circuitand the first to seventh input terminals is provided, and in asemiconductor circuit element group for constituting the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.
 13. A variable function information processor, wherein aplurality of the variable function information processors according toclaim 3 are provided and electrically connected to one another directlyor via a semiconductor arithmetic circuit, whereby a new input terminalgroup is formed by a plurality of input terminals through which inputsignals are allowed to be inputted from the outside to the variablefunction information processor, and a new output terminal group isformed by a plurality of output terminals through which output signalsare allowed to be outputted from the variable function informationprocessor to the outside, and wherein a function of serving both as acombinational logic circuit and a sequential circuit according to theinput signals inputted from the input terminal group is provided, and ina semiconductor circuit element group to constitute the combinationallogic circuit and the sequential circuit, a common part of thecombinational logic circuit and the sequential circuit is used for boththe circuits.
 14. A variable function information processor, comprising:at least one basic circuit block composed of a two-input arithmeticcircuit, to which a first signal is inputted as one input signal from afirst input terminal, for outputting an operation result of a logicaloperation of the first signal and the other input signal or an invertedsignal of the other input signal according to the first signal, aninverter for inverting the output signal of the two-input arithmeticcircuit, a switching circuit for selectively supplying an output signalof the inverter or a second signal inputted from a second input terminalas the other input signal to the two-input a rithmetic circuit inaccordance with a third signal inputted from a third input terminal, andan output terminal capable of outputting at least either the outputsignal of the two-input arithmetic circuit or the output signal of theinverter, said basic circuit block serving both as a combinational logiccircuit and as a sequential circuit according to the input signalsinputted from the first to third input terminals, and in semiconductorcircuit elements to function as the combinational logic circuit and thesequential circuit respectively, sharing common circuit elements betweenboth the circuits.
 15. The variable function information processoraccording to claim 14, wherein a plurality of said basic circuit blocksare provided, and wherein on the occasion of subordinate connection, theoutput terminal of said basic circuit block in a preceding stage isconnected to the second input terminal of said basic circuit block in asubsequent stage.
 16. The variable function information processoraccording to claim 15, wherein the two-input arithmetic circuit is atwo-input exclusive-NOR circuit or a two-input exclusive-OR circuit. 17.The variable function information processor according to claim 16,wherein said basic circuit block functions as an adding circuit or alatch circuit according to the input signal inputted from the firstinput terminal.
 18. The variable function information processoraccording to claim 17, further comprising: a semiconductor arithmeticcircuit for performing processing in response to a signal inputted; andan external output terminal capable of outputting an output signal ofsaid semiconductor arithmetic circuit, said semiconductor arithmeticcircuit performing the processing in response to at least any one signalof the input signal inputted from the first to third input terminals oran external input terminal, the output signal of the two-inputarithmetic circuit, and the output signal of the inverter.
 19. Thevariable function information processor according to claim 18, whereinsaid semiconductor arithmetic circuit includes an output switchingcircuit for outputting the input signal inputted from the first to thirdinput terminals or the external input terminal according to at leasteither the output signal of the two-input arithmetic circuit or theoutput signal of the inverter.